From c3c3e453ff4e6d73b52d88ab08a708610997f334 Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Fri, 13 Nov 2020 21:35:19 -0800 Subject: soc/intel/tigerlake: Fix overlapping memory address used for early GSPI2 and UART bars BAR address used during early initilization of GPSI 2 is overlapping with UART bar. //For GSPI2 this is the address calculated GSPI_BUS_BASE(0xFE030000,2)=0xFE032000 GSPI_BUS_BASE(bar, bus) ((bar) + (bus) * 4 * KiB) //overlaps with CONSOLE_UART_BASE_ADDRESS -> 0xfe032000 Change-Id: Id9f2140a6dd21c2cb8d75823cc83cced0c660179 Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/c/coreboot/+/47643 Tested-by: build bot (Jenkins) Reviewed-by: Anil Kumar K Reviewed-by: Furquan Shaikh Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index e962e4cccc..b97b92e46d 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -168,7 +168,7 @@ config SOC_INTEL_UART_DEV_MAX config CONSOLE_UART_BASE_ADDRESS hex - default 0xfe032000 + default 0xfe03e000 depends on INTEL_LPSS_UART_FOR_CONSOLE # Clock divider parameters for 115200 baud rate -- cgit v1.2.3