From c4e41937150beab78ba5d492b7b22799d20a0ee4 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 1 Nov 2018 11:29:50 +0100 Subject: src: Add missing include Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/29403 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/arch/x86/include/arch/registers.h | 2 ++ src/cpu/ti/am335x/uart.h | 2 ++ src/drivers/i2c/max98373/chip.h | 3 +++ src/drivers/i2c/rt5663/chip.h | 3 +++ src/drivers/i2c/w83795/chip.h | 2 ++ src/drivers/intel/fsp2_0/include/fsp/upd.h | 2 ++ src/drivers/net/chip.h | 2 ++ src/drivers/parade/ps8625/ps8625.h | 2 ++ src/drivers/siemens/nc_fpga/nc_fpga.h | 2 ++ src/include/cpu/amd/vr.h | 2 ++ src/include/device/path.h | 2 ++ src/include/swab.h | 9 ++++++--- src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h | 2 ++ src/mainboard/google/urara/urara_boardid.h | 2 ++ src/mainboard/pcengines/apu1/gpio_ftns.h | 2 ++ src/northbridge/intel/e7505/raminit.h | 2 ++ src/northbridge/intel/haswell/pei_data.h | 2 ++ src/northbridge/intel/sandybridge/pei_data.h | 2 ++ src/security/tpm/tss/tcg-1.2/tss_commands.h | 2 ++ src/security/tpm/tss/tcg-1.2/tss_internal.h | 2 ++ src/security/tpm/tss_errors.h | 2 ++ src/soc/broadcom/cygnus/include/soc/tz.h | 2 ++ src/soc/cavium/cn81xx/include/soc/cpu.h | 2 ++ src/soc/cavium/common/include/soc/bootblock.h | 2 ++ src/soc/intel/apollolake/include/soc/usb.h | 2 ++ src/soc/intel/broadwell/chip.h | 2 ++ src/soc/intel/cannonlake/include/soc/ebda.h | 2 ++ src/soc/intel/denverton_ns/chip.h | 2 ++ src/soc/intel/icelake/include/soc/ebda.h | 2 ++ src/soc/intel/quark/include/soc/i2c.h | 2 ++ src/soc/intel/skylake/include/soc/ebda.h | 2 ++ src/soc/nvidia/tegra210/include/soc/flow_ctrl.h | 2 ++ src/soc/qualcomm/ipq806x/include/soc/ebi2.h | 2 ++ src/southbridge/intel/bd82x6x/chip.h | 2 ++ src/southbridge/intel/fsp_bd82x6x/chip.h | 2 ++ src/southbridge/intel/fsp_i89xx/chip.h | 2 ++ src/southbridge/intel/i82801dx/chip.h | 2 ++ src/southbridge/intel/i82801gx/chip.h | 2 ++ src/southbridge/intel/i82801ix/chip.h | 2 ++ src/southbridge/intel/i82801jx/chip.h | 2 ++ src/southbridge/intel/lynxpoint/chip.h | 2 ++ src/superio/nuvoton/npcd378/npcd378.h | 2 ++ 42 files changed, 90 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/arch/x86/include/arch/registers.h b/src/arch/x86/include/arch/registers.h index 08f83ac091..1d3b90aa93 100644 --- a/src/arch/x86/include/arch/registers.h +++ b/src/arch/x86/include/arch/registers.h @@ -17,6 +17,8 @@ #define __ARCH_REGISTERS_H #if !defined(__ASSEMBLER__) +#include + #define DOWNTO8(A) \ union { \ struct { \ diff --git a/src/cpu/ti/am335x/uart.h b/src/cpu/ti/am335x/uart.h index 000a45dbf7..fe9197f1e1 100644 --- a/src/cpu/ti/am335x/uart.h +++ b/src/cpu/ti/am335x/uart.h @@ -15,6 +15,8 @@ #ifndef AM335X_UART_H #define AM335X_UART_H +#include + #define AM335X_UART0_BASE 0x44e09000 #define AM335X_UART1_BASE 0x48020000 #define AM335X_UART2_BASE 0x48024000 diff --git a/src/drivers/i2c/max98373/chip.h b/src/drivers/i2c/max98373/chip.h index ad81395238..dcaf3570cc 100644 --- a/src/drivers/i2c/max98373/chip.h +++ b/src/drivers/i2c/max98373/chip.h @@ -16,6 +16,9 @@ /* * Maxim MAX98373 audio codec devicetree bindings */ + +#include + struct drivers_i2c_max98373_config { /* I2C Bus Frequency in Hertz (default 400kHz) */ uint32_t bus_speed; diff --git a/src/drivers/i2c/rt5663/chip.h b/src/drivers/i2c/rt5663/chip.h index 1b367c934f..5720b185a3 100644 --- a/src/drivers/i2c/rt5663/chip.h +++ b/src/drivers/i2c/rt5663/chip.h @@ -16,6 +16,9 @@ /* * Realtek RT5663 audio codec devicetree bindings */ + +#include + struct drivers_i2c_rt5663_config { /* I2C Bus Frequency in Hertz (default 400kHz) */ unsigned int bus_speed; diff --git a/src/drivers/i2c/w83795/chip.h b/src/drivers/i2c/w83795/chip.h index b48c5231b1..e3426dec5c 100644 --- a/src/drivers/i2c/w83795/chip.h +++ b/src/drivers/i2c/w83795/chip.h @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include + struct drivers_i2c_w83795_config { uint8_t fanin_ctl1; uint8_t fanin_ctl2; diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h index 15094dfb10..19c542307e 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/upd.h +++ b/src/drivers/intel/fsp2_0/include/fsp/upd.h @@ -12,6 +12,8 @@ #ifndef _FSP2_0_UPD_H_ #define _FSP2_0_UPD_H_ +#include + struct FSP_UPD_HEADER { /// /// UPD Region Signature. This signature will be diff --git a/src/drivers/net/chip.h b/src/drivers/net/chip.h index 383614f514..985a85aac8 100644 --- a/src/drivers/net/chip.h +++ b/src/drivers/net/chip.h @@ -14,6 +14,8 @@ #ifndef __DRIVERS_R8168_CHIP_H__ #define __DRIVERS_R8168_CHIP_H__ +#include + struct drivers_net_config { uint16_t customized_leds; unsigned wake; /* Wake pin for ACPI _PRW */ diff --git a/src/drivers/parade/ps8625/ps8625.h b/src/drivers/parade/ps8625/ps8625.h index 1fbb01cb43..a5132f1244 100644 --- a/src/drivers/parade/ps8625/ps8625.h +++ b/src/drivers/parade/ps8625/ps8625.h @@ -16,6 +16,8 @@ #ifndef __PS8625_H__ #define __PS8625_H__ +#include + struct parade_write { uint8_t offset; uint8_t reg; diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.h b/src/drivers/siemens/nc_fpga/nc_fpga.h index fe5f612a83..f1982d2e38 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.h +++ b/src/drivers/siemens/nc_fpga/nc_fpga.h @@ -16,6 +16,8 @@ #ifndef _SIEMENS_NC_FPGA_H_ #define _SIEMENS_NC_FPGA_H_ +#include + #define NC_MAGIC_OFFSET 0x020 #define NC_FPGA_MAGIC 0x4E433746 #define NC_CAP1_OFFSET 0x080 diff --git a/src/include/cpu/amd/vr.h b/src/include/cpu/amd/vr.h index e5ab840b58..8c62e442b5 100644 --- a/src/include/cpu/amd/vr.h +++ b/src/include/cpu/amd/vr.h @@ -7,6 +7,8 @@ #ifndef CPU_AMD_VR_H #define CPU_AMD_VR_H +#include + #define VRC_INDEX 0xAC1C // Index register #define VRC_DATA 0xAC1E // Data register #define VR_UNLOCK 0xFC53 // Virtual register unlock code diff --git a/src/include/device/path.h b/src/include/device/path.h index 0d9c681c88..6736bede69 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -1,6 +1,8 @@ #ifndef DEVICE_PATH_H #define DEVICE_PATH_H +#include + enum device_path_type { DEVICE_PATH_NONE = 0, DEVICE_PATH_ROOT, diff --git a/src/include/swab.h b/src/include/swab.h index 7d781a089e..956cfa5532 100644 --- a/src/include/swab.h +++ b/src/include/swab.h @@ -1,6 +1,3 @@ -#ifndef _SWAB_H -#define _SWAB_H - /* * linux/byteorder/swab.h * Byte-swapping, independently from CPU endianness @@ -18,6 +15,12 @@ /* casts are necessary for constants, because we never know how for sure * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way. */ + +#ifndef _SWAB_H +#define _SWAB_H + +#include + #define swab16(x) \ ((unsigned short)( \ (((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \ diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h index 903ebaa3a0..8f1e24ccfa 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h @@ -17,6 +17,8 @@ * Copyed over from qemu soure tree, include/hw/nvram/fw_cfg.h */ +#include + #define FW_CFG_SIGNATURE 0x00 #define FW_CFG_ID 0x01 #define FW_CFG_UUID 0x02 diff --git a/src/mainboard/google/urara/urara_boardid.h b/src/mainboard/google/urara/urara_boardid.h index 7c7c04584e..fbd9179a8a 100644 --- a/src/mainboard/google/urara/urara_boardid.h +++ b/src/mainboard/google/urara/urara_boardid.h @@ -16,6 +16,8 @@ #ifndef __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__ #define __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__ +#include + /* * List of URARA derivatives board ID definitions. They are stored in uint8_t * across the code, using #defines here not to imply any specific size. diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.h b/src/mainboard/pcengines/apu1/gpio_ftns.h index 8eadebd408..fce8afe6f0 100644 --- a/src/mainboard/pcengines/apu1/gpio_ftns.h +++ b/src/mainboard/pcengines/apu1/gpio_ftns.h @@ -16,6 +16,8 @@ #ifndef GPIO_FTNS_H #define GPIO_FTNS_H +#include + uintptr_t find_gpio_base(void); void configure_gpio(uintptr_t base_addr, u32 gpio, u8 iomux_ftn, u8 setting); u8 read_gpio(uintptr_t base_addr, u32 gpio); diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index 1581b826b8..cdfc92a965 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -14,6 +14,8 @@ #ifndef RAMINIT_H #define RAMINIT_H +#include + #define MAX_DIMM_SOCKETS_PER_CHANNEL 4 #define MAX_NUM_CHANNELS 2 #define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL) diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h index 319b9e76f0..dfc34d8ce9 100644 --- a/src/northbridge/intel/haswell/pei_data.h +++ b/src/northbridge/intel/haswell/pei_data.h @@ -30,6 +30,8 @@ #ifndef PEI_DATA_H #define PEI_DATA_H +#include + typedef void (*tx_byte_func)(unsigned char byte); #define PEI_VERSION 15 diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index 00534ca9a7..0a60707136 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -30,6 +30,8 @@ #ifndef PEI_DATA_H #define PEI_DATA_H +#include + typedef struct { uint16_t mode; // 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto uint16_t hs_port_switch_mask; // 4 bit mask, 1: switchable, 0: not switchable diff --git a/src/security/tpm/tss/tcg-1.2/tss_commands.h b/src/security/tpm/tss/tcg-1.2/tss_commands.h index 9d30bfc2a2..acdc8be713 100644 --- a/src/security/tpm/tss/tcg-1.2/tss_commands.h +++ b/src/security/tpm/tss/tcg-1.2/tss_commands.h @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include + const struct s_tpm_extend_cmd{ uint8_t buffer[34]; uint16_t pcrNum; diff --git a/src/security/tpm/tss/tcg-1.2/tss_internal.h b/src/security/tpm/tss/tcg-1.2/tss_internal.h index 01912bb78e..e999cb947f 100644 --- a/src/security/tpm/tss/tcg-1.2/tss_internal.h +++ b/src/security/tpm/tss/tcg-1.2/tss_internal.h @@ -6,6 +6,8 @@ #ifndef TCG_TSS_INTERNAL_H_ #define TCG_TSS_INTERNAL_H_ +#include + /* * These numbers derive from adding the sizes of command fields as shown in the * TPM commands manual. diff --git a/src/security/tpm/tss_errors.h b/src/security/tpm/tss_errors.h index c80ffa15f3..316661cd0a 100644 --- a/src/security/tpm/tss_errors.h +++ b/src/security/tpm/tss_errors.h @@ -12,6 +12,8 @@ #ifndef TSS_ERRORS_H_ #define TSS_ERRORS_H_ +#include + #define TPM_E_BASE 0x0 #define TPM_E_NON_FATAL 0x800 diff --git a/src/soc/broadcom/cygnus/include/soc/tz.h b/src/soc/broadcom/cygnus/include/soc/tz.h index a6777fda41..1d5d234e29 100644 --- a/src/soc/broadcom/cygnus/include/soc/tz.h +++ b/src/soc/broadcom/cygnus/include/soc/tz.h @@ -14,6 +14,8 @@ #ifndef __SOC_BROADCOM_CYGNUS_TZ_H__ #define __SOC_BROADCOM_CYGNUS_TZ_H__ +#include + #define TZ_STATE_SECURE 0 #define TZ_STATE_NON_SECURE 1 diff --git a/src/soc/cavium/cn81xx/include/soc/cpu.h b/src/soc/cavium/cn81xx/include/soc/cpu.h index b2472d78e3..1c6a30dda9 100644 --- a/src/soc/cavium/cn81xx/include/soc/cpu.h +++ b/src/soc/cavium/cn81xx/include/soc/cpu.h @@ -17,6 +17,8 @@ #ifndef __SOC_CAVIUM_CN81XX_CPU_H__ #define __SOC_CAVIUM_CN81XX_CPU_H__ +#include + /** * Number of the Core on which the program is currently running. * diff --git a/src/soc/cavium/common/include/soc/bootblock.h b/src/soc/cavium/common/include/soc/bootblock.h index 76fd4a158d..1df444fad2 100644 --- a/src/soc/cavium/common/include/soc/bootblock.h +++ b/src/soc/cavium/common/include/soc/bootblock.h @@ -16,6 +16,8 @@ #ifndef SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_BOOTBLOCK_H_ #define SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_BOOTBLOCK_H_ +#include + void bootblock_mainboard_early_init(void); void bootblock_soc_early_init(void); void bootblock_soc_init(void); diff --git a/src/soc/intel/apollolake/include/soc/usb.h b/src/soc/intel/apollolake/include/soc/usb.h index 7220023199..7dd9ec089a 100644 --- a/src/soc/intel/apollolake/include/soc/usb.h +++ b/src/soc/intel/apollolake/include/soc/usb.h @@ -18,6 +18,8 @@ #ifndef _SOC_APOLLOLAKE_USB_H_ #define _SOC_APOLLOLAKE_USB_H_ +#include + #define APOLLOLAKE_USB2_PORT_MAX 8 struct usb2_eye_per_port { diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 46c2c1d8ba..0885c2dd5b 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -17,6 +17,8 @@ #ifndef _SOC_INTEL_BROADWELL_CHIP_H_ #define _SOC_INTEL_BROADWELL_CHIP_H_ +#include + struct soc_intel_broadwell_config { /* * Interrupt Routing configuration diff --git a/src/soc/intel/cannonlake/include/soc/ebda.h b/src/soc/intel/cannonlake/include/soc/ebda.h index 15a9d28a91..ad62394588 100644 --- a/src/soc/intel/cannonlake/include/soc/ebda.h +++ b/src/soc/intel/cannonlake/include/soc/ebda.h @@ -16,6 +16,8 @@ #ifndef SOC_EBDA_H #define SOC_EBDA_H +#include + struct ebda_config { uint32_t signature; /* 0x00 - EBDA signature */ uint32_t tolum_base; /* 0x04 - coreboot memory start */ diff --git a/src/soc/intel/denverton_ns/chip.h b/src/soc/intel/denverton_ns/chip.h index bfa6a0132f..f2a67dd9f9 100644 --- a/src/soc/intel/denverton_ns/chip.h +++ b/src/soc/intel/denverton_ns/chip.h @@ -17,6 +17,8 @@ #ifndef SOC_INTEL_DENVERTON_NS_CHIP_H #define SOC_INTEL_DENVERTON_NS_CHIP_H +#include + struct soc_intel_denverton_ns_config { /** * Interrupt Routing configuration diff --git a/src/soc/intel/icelake/include/soc/ebda.h b/src/soc/intel/icelake/include/soc/ebda.h index 9c44a50831..f4d89e993d 100644 --- a/src/soc/intel/icelake/include/soc/ebda.h +++ b/src/soc/intel/icelake/include/soc/ebda.h @@ -16,6 +16,8 @@ #ifndef SOC_EBDA_H #define SOC_EBDA_H +#include + struct ebda_config { uint32_t signature; /* 0x00 - EBDA signature */ uint32_t tolum_base; /* 0x04 - coreboot memory start */ diff --git a/src/soc/intel/quark/include/soc/i2c.h b/src/soc/intel/quark/include/soc/i2c.h index 85ae7b9e3e..f3c585f737 100644 --- a/src/soc/intel/quark/include/soc/i2c.h +++ b/src/soc/intel/quark/include/soc/i2c.h @@ -16,6 +16,8 @@ #ifndef _QUARK_I2C_H_ #define _QUARK_I2C_H_ +#include + typedef volatile struct _I2C_REGS { volatile uint32_t ic_con; /* 00: Control Register */ volatile uint32_t ic_tar; /* 04: Master Target Address */ diff --git a/src/soc/intel/skylake/include/soc/ebda.h b/src/soc/intel/skylake/include/soc/ebda.h index 15a9d28a91..ad62394588 100644 --- a/src/soc/intel/skylake/include/soc/ebda.h +++ b/src/soc/intel/skylake/include/soc/ebda.h @@ -16,6 +16,8 @@ #ifndef SOC_EBDA_H #define SOC_EBDA_H +#include + struct ebda_config { uint32_t signature; /* 0x00 - EBDA signature */ uint32_t tolum_base; /* 0x04 - coreboot memory start */ diff --git a/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h b/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h index 2dd1f9f3b1..602c75c5fe 100644 --- a/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h +++ b/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h @@ -16,6 +16,8 @@ #ifndef _TEGRA210_FLOW_CTRL_H_ #define _TEGRA210_FLOW_CTRL_H_ +#include + void flowctrl_cpu_off(int cpu); void flowctrl_cpu_on(int cpu); void flowctrl_cpu_suspend(int cpu); diff --git a/src/soc/qualcomm/ipq806x/include/soc/ebi2.h b/src/soc/qualcomm/ipq806x/include/soc/ebi2.h index 3e99c3bd26..5dcd9b858f 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/ebi2.h +++ b/src/soc/qualcomm/ipq806x/include/soc/ebi2.h @@ -19,6 +19,8 @@ #ifndef __SOC_QUALCOMM_IPQ806X_EBI2_H_ #define __SOC_QUALCOMM_IPQ806X_EBI2_H_ +#include + #define EBI2CR_BASE (0x1A600000) struct ebi2cr_regs { diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index ce8a804d50..29f6881fc2 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -16,6 +16,8 @@ #ifndef SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H #define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H +#include + struct southbridge_intel_bd82x6x_config { /** * GPI Routing configuration diff --git a/src/southbridge/intel/fsp_bd82x6x/chip.h b/src/southbridge/intel/fsp_bd82x6x/chip.h index 9d6a9e4dbd..8da39368f5 100644 --- a/src/southbridge/intel/fsp_bd82x6x/chip.h +++ b/src/southbridge/intel/fsp_bd82x6x/chip.h @@ -16,6 +16,8 @@ #ifndef SOUTHBRIDGE_INTEL_FSP_BD82X6X_CHIP_H #define SOUTHBRIDGE_INTEL_FSP_BD82X6X_CHIP_H +#include + struct southbridge_intel_fsp_bd82x6x_config { /** * Interrupt Routing configuration diff --git a/src/southbridge/intel/fsp_i89xx/chip.h b/src/southbridge/intel/fsp_i89xx/chip.h index 69e1dc77cf..bea3e072f2 100644 --- a/src/southbridge/intel/fsp_i89xx/chip.h +++ b/src/southbridge/intel/fsp_i89xx/chip.h @@ -16,6 +16,8 @@ #ifndef SOUTHBRIDGE_INTEL_I89XX_CHIP_H #define SOUTHBRIDGE_INTEL_I89XX_CHIP_H +#include + struct southbridge_intel_fsp_i89xx_config { /** * Interrupt Routing configuration diff --git a/src/southbridge/intel/i82801dx/chip.h b/src/southbridge/intel/i82801dx/chip.h index f77413d671..a0961ee76d 100644 --- a/src/southbridge/intel/i82801dx/chip.h +++ b/src/southbridge/intel/i82801dx/chip.h @@ -17,6 +17,8 @@ #ifndef I82801DX_CHIP_H #define I82801DX_CHIP_H +#include + struct southbridge_intel_i82801dx_config { int enable_usb; int enable_native_ide; diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index e89fcc4d05..3a20ab1cb3 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -16,6 +16,8 @@ #ifndef SOUTHBRIDGE_INTEL_I82801GX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H +#include + struct southbridge_intel_i82801gx_config { /** * Interrupt Routing configuration diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index 307b751fab..0b3e0b5a50 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -17,6 +17,8 @@ #ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H +#include + enum { THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3, THTL_50_0 = 4, THTL_37_5 = 5, THTL_25_0 = 6, THTL_12_5 = 7 diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index 533254a872..1712b8162c 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -17,6 +17,8 @@ #ifndef SOUTHBRIDGE_INTEL_I82801JX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801JX_CHIP_H +#include + enum { THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3, THTL_50_0 = 4, THTL_37_5 = 5, THTL_25_0 = 6, THTL_12_5 = 7 diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index d11ce5fcee..09f1c90469 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -16,6 +16,8 @@ #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H #define SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H +#include + struct southbridge_intel_lynxpoint_config { /** * Interrupt Routing configuration diff --git a/src/superio/nuvoton/npcd378/npcd378.h b/src/superio/nuvoton/npcd378/npcd378.h index 53541a9efb..cf0b804753 100644 --- a/src/superio/nuvoton/npcd378/npcd378.h +++ b/src/superio/nuvoton/npcd378/npcd378.h @@ -17,6 +17,8 @@ #ifndef SUPERIO_NUVOTON_NPCD378_H #define SUPERIO_NUVOTON_NPCD378_H +#include + /* HWM at LDN8 */ #define NPCD837_HWM_WRITE_LOCK_CTRL 0x4 #define NPCD837_HWM_WRITE_LOCK_BIT 0x1 -- cgit v1.2.3