From ca2f68abedcc2065574a03a4525b1c3cab7280ba Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 22 Mar 2020 13:15:12 +0100 Subject: nb/intel/sandybridge: Correct TC_DTP handling It is only for Ivy Bridge, and needs to be set on certain circumstances. Change-Id: I4093adef44fae787c96fec4b4b8c7c867786d219 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39760 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/intel/sandybridge/raminit_common.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 620c57404a..9e27400942 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -216,8 +216,22 @@ void dram_timing_regs(ramctr_timing *ctrl) printram("OTHP [%x] = %x\n", addr, reg); MCHBAR32(addr) = reg; - /* FIXME: This register only exists on Ivy Bridge! */ - MCHBAR32(TC_DTP_ch(channel)) = 0; + /* Debug parameters - only applies to Ivy Bridge */ + if (IS_IVY_CPU(ctrl->cpu)) { + reg = 0; + + /* + * If tXP and tXPDLL are very high, we need to increase them by one. + * This can only happen on Ivy Bridge, and when overclocking the RAM. + */ + if (ctrl->tXP >= 8) + reg |= (1 << 12); + + if (ctrl->tXPDLL >= 32) + reg |= (1 << 13); + + MCHBAR32(TC_DTP_ch(channel)) = reg; + } MCHBAR32_OR(addr, 0x00020000); -- cgit v1.2.3