From cc394d4d37533a4977c1da629c8ebf405a91d32a Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Thu, 10 Jan 2019 21:52:39 +0800
Subject: mb/google/sarien/variants/sarien: Set up tcc offset for sarien

Change tcc offset from 15 to 3 for sarien.

BUG=b:122636962
TEST=Match the result from TAT UI

Change-Id: I1c5d144e92d1e6e9c81b3e6686805ccf744b7203
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30808
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/sarien/variants/sarien/devicetree.cb | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src')

diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 37ef3dc5e0..4334c45083 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -74,6 +74,9 @@ chip soc/intel/cannonlake
 	#| I2C1              | Touchpad                  |
 	#| I2C4              | H1 TPM                    |
 	#+-------------------+---------------------------+
+
+	register "tcc_offset" = "3"
+
 	register "common_soc_config" = "{
 		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 		.i2c[0] = {
-- 
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