From ce2c1cb742b17623978f3d9a9e414552189bc819 Mon Sep 17 00:00:00 2001 From: Jett Rink Date: Wed, 15 May 2019 13:40:05 -0600 Subject: mb/google/sarien: leave gpio pads unlocks during fsp The FSP will lock down the configuration of GPP_A12, which makes the configuration of the GPIO pin on warm reset not work correctly. This is only needed for the Arcada variant since it is the only variant that uses ISH. BRANCH=sarien BUG=b:132719369 TEST=ISH_GP6 now works on warm resets on arcarda Change-Id: Icb3bae2c48eee053189f1a878f5975c6afe51c71 Signed-off-by: Jett Rink Reviewed-on: https://review.coreboot.org/c/coreboot/+/32831 Reviewed-by: Furquan Shaikh Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- src/mainboard/google/sarien/variants/arcada/devicetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 27c61f3563..b6377ba55d 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -26,6 +26,7 @@ chip soc/intel/cannonlake register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s register "PchPmSlpAMinAssert" = "4" # 2s + register "PchUnlockGpioPads" = "1" register "speed_shift_enable" = "1" register "psys_pmax" = "140" -- cgit v1.2.3