From d2186a3b3f5c092a97bd2b669a846f73441353d9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Thu, 26 Sep 2019 09:49:00 +0300
Subject: soc/intel/fsp_broadwell_de: Enable SSE and SSE2
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Apparently romcc-bootblock just barely built without
XMM registers.

Change-Id: Ie7b1101f47c2dfb718bef99f8c05f9d575c821cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
---
 src/soc/intel/fsp_broadwell_de/Kconfig | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src')

diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig
index 94eff07bab..6c74a749a4 100644
--- a/src/soc/intel/fsp_broadwell_de/Kconfig
+++ b/src/soc/intel/fsp_broadwell_de/Kconfig
@@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS
 	select PARALLEL_MP
 	select SMP
 	select IOAPIC
+	select SSE2
 	select UDELAY_TSC
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
-- 
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