From d3f01b21fa7bf9bf115088ddc032aa1cd0000945 Mon Sep 17 00:00:00 2001 From: Tristan Corrick Date: Thu, 6 Dec 2018 22:46:58 +1300 Subject: sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The H81 chipset is the only non-LP Lynx Point chipset with 6 PCIe root ports, all others have 8 [1]. The existing PCIe code assumed that all non-LP chipsets had 8 root ports, which meant that port 6 would not be considered the last root port on H81, so `root_port_commit_config()` would not run. Ultimately, while PCIe still worked on H81, all the root ports would remain enabled, even if disabled in the devicetree. Also, remove `PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_{MIN,MAX}`, as they are unused, and the MAX constant is incorrect. Interestingly, this fixes an issue where GRUB is unable to halt the system. Tested on an ASRock H81M-HDS. The root ports disabled in the devicetree do indeed end up disabled. [1] Intel® 8 Series/C220 Series Chipset Family Platform Controller Hub (PCH) Datasheet, revision 003, document number 328904. Change-Id: If3ce217e8a4f4ea4e111e4525b03dbbfc63f92b0 Signed-off-by: Tristan Corrick Reviewed-on: https://review.coreboot.org/c/30077 Reviewed-by: Arthur Heymans Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/include/device/pci_ids.h | 23 +++++++++++++++++++---- src/mainboard/asrock/h81m-hds/devicetree.cb | 2 -- src/southbridge/intel/lynxpoint/pch.c | 10 ++++++++++ src/southbridge/intel/lynxpoint/pch.h | 1 + src/southbridge/intel/lynxpoint/pcie.c | 17 ++++++++--------- 5 files changed, 38 insertions(+), 15 deletions(-) (limited to 'src') diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index b9c915239d..751cca0289 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2661,11 +2661,26 @@ #define PCI_DEVICE_ID_INTEL_PCIE_PB 0x3597 #define PCI_DEVICE_ID_INTEL_PCIE_PC 0x3599 -/* Intel Lynx Point Device IDS */ -#define PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MIN 0x8c41 -#define PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MAX 0x8c4f - /* Intel LPC device ids */ +#define PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE 0x8c41 +#define PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE 0x8c42 +#define PCI_DEVICE_ID_INTEL_LPT_Z87 0x8c44 +#define PCI_DEVICE_ID_INTEL_LPT_Z85 0x8c46 +#define PCI_DEVICE_ID_INTEL_LPT_HM86 0x8c49 +#define PCI_DEVICE_ID_INTEL_LPT_H87 0x8c4a +#define PCI_DEVICE_ID_INTEL_LPT_HM87 0x8c4b +#define PCI_DEVICE_ID_INTEL_LPT_Q85 0x8c4c +#define PCI_DEVICE_ID_INTEL_LPT_Q87 0x8c4e +#define PCI_DEVICE_ID_INTEL_LPT_QM87 0x8c4f +#define PCI_DEVICE_ID_INTEL_LPT_B85 0x8c50 +#define PCI_DEVICE_ID_INTEL_LPT_C222 0x8c52 +#define PCI_DEVICE_ID_INTEL_LPT_C224 0x8c54 +#define PCI_DEVICE_ID_INTEL_LPT_C226 0x8c56 +#define PCI_DEVICE_ID_INTEL_LPT_H81 0x8c5c +#define PCI_DEVICE_ID_INTEL_LPT_LP_SAMPLE 0x9c41 +#define PCI_DEVICE_ID_INTEL_LPT_LP_PREMIUM 0x9c43 +#define PCI_DEVICE_ID_INTEL_LPT_LP_MAINSTREAM 0x9c45 +#define PCI_DEVICE_ID_INTEL_LPT_LP_VALUE 0x9c47 #define PCI_DEVICE_ID_INTEL_SPT_LP_SAMPLE 0x9d41 #define PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE 0x9d43 #define PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM 0x9d48 diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb index 32b5978092..58a319d086 100644 --- a/src/mainboard/asrock/h81m-hds/devicetree.cb +++ b/src/mainboard/asrock/h81m-hds/devicetree.cb @@ -102,8 +102,6 @@ chip northbridge/intel/haswell device pci 1c.5 on # PCIe 1x slot subsystemid 0x1849 0x8c1a end - device pci 1c.6 off end # PCIe port #7 - device pci 1c.7 off end # PCIe port #8 device pci 1d.0 on # EHCI controller #1 subsystemid 0x1849 0x8c26 end diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 6596aa2f5d..1fb6d7ad54 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -45,6 +45,16 @@ int pch_silicon_revision(void) return pch_revision_id; } +int pch_silicon_id(void) +{ + static int pch_id = -1; + + if (pch_id < 0) + pch_id = pci_read_config16(pch_get_lpc_device(), PCI_DEVICE_ID); + + return pch_id; +} + int pch_silicon_type(void) { static int pch_type = -1; diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index a28d703130..ee041d9dd2 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -141,6 +141,7 @@ struct rcba_config_instruction #if !defined(__ASSEMBLER__) void pch_config_rcba(const struct rcba_config_instruction *rcba_config); int pch_silicon_revision(void); +int pch_silicon_id(void); int pch_silicon_type(void); int pch_is_lp(void); u16 get_pmbase(void); diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 70bfe18242..750b53395c 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -23,10 +23,7 @@ #include "pch.h" #include -/* LynxPoint-LP has 6 root ports while non-LP has 8. */ #define MAX_NUM_ROOT_PORTS 8 -#define H_NUM_ROOT_PORTS MAX_NUM_ROOT_PORTS -#define LP_NUM_ROOT_PORTS (MAX_NUM_ROOT_PORTS - 2) struct root_port_config { /* RPFN is a write-once register so keep a copy until it is written */ @@ -49,10 +46,10 @@ static struct root_port_config rpc; static inline int max_root_ports(void) { - if (pch_is_lp()) - return LP_NUM_ROOT_PORTS; - else - return H_NUM_ROOT_PORTS; + if (pch_is_lp() || pch_silicon_id() == PCI_DEVICE_ID_INTEL_LPT_H81) + return 6; + + return 8; } static inline int root_port_is_first(struct device *dev) @@ -208,8 +205,10 @@ static void pcie_enable_clock_gating(void) pci_update_config8(dev, 0xe1, 0x7f, 0x80); } if (rp == 5 && !rpc.ports[5]->enabled && - !rpc.ports[6]->enabled && - !rpc.ports[7]->enabled) { + (rpc.ports[6] == NULL || + !rpc.ports[6]->enabled) && + (rpc.ports[7] == NULL || + !rpc.ports[7]->enabled)) { pci_update_config8(dev, 0xe2, ~1, 1); pci_update_config8(dev, 0xe1, 0x7f, 0x80); } -- cgit v1.2.3