From d8e34b2c44605d2eb6ed1a955148ac24b9d0cd2e Mon Sep 17 00:00:00 2001 From: Teo Boon Tiong Date: Wed, 28 Dec 2016 18:56:26 +0800 Subject: driver/intel/fsp1_1: Fix boot failure for non-verstage case Currently car_stage_entry is defined only in romstage_after_verstage and as a result when SEPARATE_VERSTAGE is not selected, there is no entry point into romstage and romstage will not be started at all. The solution is move out romstage_after_verstage.S from fsp1.1 driver to skylake/romstage. And add CONFIG_PLATFORM_USES_FSP1_1 to fix the build and boot issue with this change. Besides that, rename the romstage_after_verstage to romstage_c_entry in more appropriate naming convention after this fix. Tested on SkyLake Saddle Brook (FSP 1.1) and KabyLake Rvp11 (FSP 2.0), romstage can be started successfully. Change-Id: I1cd2cf5655fdff6e23b7b76c3974e7dfd3835efd Signed-off-by: Teo Boon Tiong Reviewed-on: https://review.coreboot.org/17976 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp1_1/Makefile.inc | 1 - src/drivers/intel/fsp1_1/car.c | 2 +- src/drivers/intel/fsp1_1/include/fsp/car.h | 2 +- src/drivers/intel/fsp1_1/romstage_after_verstage.S | 38 -------------------- src/soc/intel/skylake/romstage/Makefile.inc | 1 + src/soc/intel/skylake/romstage/car_stage.S | 40 ++++++++++++++++++++++ 6 files changed, 43 insertions(+), 41 deletions(-) delete mode 100644 src/drivers/intel/fsp1_1/romstage_after_verstage.S create mode 100644 src/soc/intel/skylake/romstage/car_stage.S (limited to 'src') diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 4088293e3f..e2f75eee51 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -28,7 +28,6 @@ romstage-y += fsp_util.c romstage-y += hob.c romstage-y += raminit.c romstage-y += romstage.c -romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S romstage-y += stack.c romstage-y += stage_cache.c romstage-$(CONFIG_MMA) += mma_core.c diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 1a5f9a8333..e1a9b9db6c 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -68,7 +68,7 @@ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params) } /* Entry point taken when romstage is called after a separate verstage. */ -asmlinkage void *romstage_after_verstage(void) +asmlinkage void *romstage_c_entry(void) { /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram * is still enabled. We can directly access work buffer here. */ diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h index 88dca9a0c5..5214d73b29 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/car.h +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -32,7 +32,7 @@ struct cache_as_ram_params { /* Entry points from the cache-as-ram assembly code. */ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params); asmlinkage void after_cache_as_ram(void *chipset_context); -asmlinkage void *romstage_after_verstage(void); +asmlinkage void *romstage_c_entry(void); /* Per stage calls from the above two functions. The void * return from * cache_as_ram_stage_main() is the stack pointer to use in RAM after * exiting cache-as-ram mode. */ diff --git a/src/drivers/intel/fsp1_1/romstage_after_verstage.S b/src/drivers/intel/fsp1_1/romstage_after_verstage.S deleted file mode 100644 index 2a3372f905..0000000000 --- a/src/drivers/intel/fsp1_1/romstage_after_verstage.S +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ - -.text -.global car_stage_entry -car_stage_entry: - call romstage_after_verstage - #include "after_raminit.S" - - movb $0x69, %ah - jmp .Lhlt - -.Lhlt: - xchg %al, %ah -#if IS_ENABLED(CONFIG_POST_IO) - outb %al, $CONFIG_POST_IO_PORT -#else - post_code(POST_DEAD_CODE) -#endif - movl $LHLT_DELAY, %ecx -.Lhlt_Delay: - outb %al, $0xED - loop .Lhlt_Delay - jmp .Lhlt diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index c19301f734..47c8c7e39c 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,5 +1,6 @@ verstage-y += power_state.c +romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += car_stage.S romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += car_stage_fsp20.S romstage-y += pmc.c romstage-y += power_state.c diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/soc/intel/skylake/romstage/car_stage.S new file mode 100644 index 0000000000..9482456922 --- /dev/null +++ b/src/soc/intel/skylake/romstage/car_stage.S @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* I/O delay between post codes on failure */ +#define LHLT_DELAY 0x50000 + +.text +.global car_stage_entry +car_stage_entry: + call romstage_c_entry + #include "src/drivers/intel/fsp1_1/after_raminit.S" + + + movb $0x69, %ah + jmp .Lhlt + +.Lhlt: + xchg %al, %ah +#if IS_ENABLED(CONFIG_POST_IO) + outb %al, $CONFIG_POST_IO_PORT +#else + post_code(POST_DEAD_CODE) +#endif + movl $LHLT_DELAY, %ecx +.Lhlt_Delay: + outb %al, $0xED + loop .Lhlt_Delay + jmp .Lhlt -- cgit v1.2.3