From df248f0c10f77b4de287be7754afadce1abca84c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 12 Nov 2019 10:05:33 +0100 Subject: mb/asrock/b85m_pro4: Add new mainboard MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a µATX mainboard with a LGA1150 socket and four DDR3 DIMM slots. Working: - All four DIMM slots - Serial port to emit spam - Some USB ports - Integrated graphics (libgfxinit) - HDMI and DVI - Intel GbE - All PCIe ports - Both PCI ports behind the ASM1083 PCI bridge - At least one SATA port - RAM initialization with MRC binary - Flashing with flashrom - S3 suspend/resume - Rear audio output - VBT - SeaBIOS to boot Arch Linux Not working: - PS/2 keyboard (detected as mouse) Untested: - The other audio jacks - S/PDIF - VGA - EHCI debug - Front USB headers - Non-Linux OSes - TPM header - Parallel port Change-Id: I10a16dfc56f2aa88648c8aaaba4feab40c491504 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/36770 Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/mainboard/asrock/b85m_pro4/Kconfig | 47 ++++++ src/mainboard/asrock/b85m_pro4/Kconfig.name | 2 + src/mainboard/asrock/b85m_pro4/Makefile.inc | 5 + src/mainboard/asrock/b85m_pro4/acpi/ec.asl | 0 src/mainboard/asrock/b85m_pro4/acpi/platform.asl | 23 +++ src/mainboard/asrock/b85m_pro4/acpi/superio.asl | 26 +++ src/mainboard/asrock/b85m_pro4/acpi_tables.c | 21 +++ src/mainboard/asrock/b85m_pro4/board_info.txt | 7 + src/mainboard/asrock/b85m_pro4/bootblock.c | 43 +++++ src/mainboard/asrock/b85m_pro4/cmos.default | 4 + src/mainboard/asrock/b85m_pro4/cmos.layout | 65 ++++++++ src/mainboard/asrock/b85m_pro4/data.vbt | Bin 0 -> 6144 bytes src/mainboard/asrock/b85m_pro4/devicetree.cb | 119 ++++++++++++++ src/mainboard/asrock/b85m_pro4/dsdt.asl | 40 +++++ src/mainboard/asrock/b85m_pro4/gma-mainboard.ads | 30 ++++ src/mainboard/asrock/b85m_pro4/gpio.c | 196 +++++++++++++++++++++++ src/mainboard/asrock/b85m_pro4/hda_verb.c | 63 ++++++++ src/mainboard/asrock/b85m_pro4/romstage.c | 100 ++++++++++++ 18 files changed, 791 insertions(+) create mode 100644 src/mainboard/asrock/b85m_pro4/Kconfig create mode 100644 src/mainboard/asrock/b85m_pro4/Kconfig.name create mode 100644 src/mainboard/asrock/b85m_pro4/Makefile.inc create mode 100644 src/mainboard/asrock/b85m_pro4/acpi/ec.asl create mode 100644 src/mainboard/asrock/b85m_pro4/acpi/platform.asl create mode 100644 src/mainboard/asrock/b85m_pro4/acpi/superio.asl create mode 100644 src/mainboard/asrock/b85m_pro4/acpi_tables.c create mode 100644 src/mainboard/asrock/b85m_pro4/board_info.txt create mode 100644 src/mainboard/asrock/b85m_pro4/bootblock.c create mode 100644 src/mainboard/asrock/b85m_pro4/cmos.default create mode 100644 src/mainboard/asrock/b85m_pro4/cmos.layout create mode 100644 src/mainboard/asrock/b85m_pro4/data.vbt create mode 100644 src/mainboard/asrock/b85m_pro4/devicetree.cb create mode 100644 src/mainboard/asrock/b85m_pro4/dsdt.asl create mode 100644 src/mainboard/asrock/b85m_pro4/gma-mainboard.ads create mode 100644 src/mainboard/asrock/b85m_pro4/gpio.c create mode 100644 src/mainboard/asrock/b85m_pro4/hda_verb.c create mode 100644 src/mainboard/asrock/b85m_pro4/romstage.c (limited to 'src') diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig new file mode 100644 index 0000000000..91ae3a5b24 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/Kconfig @@ -0,0 +1,47 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Tristan Corrick +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_ASROCK_B85M_PRO4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_HASWELL + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + +config MAINBOARD_DIR + string + default asrock/b85m_pro4 + +config MAINBOARD_PART_NUMBER + string + default "B85M Pro4" + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig.name b/src/mainboard/asrock/b85m_pro4/Kconfig.name new file mode 100644 index 0000000000..4bb4dfd985 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_B85M_PRO4 + bool "B85M Pro4" diff --git a/src/mainboard/asrock/b85m_pro4/Makefile.inc b/src/mainboard/asrock/b85m_pro4/Makefile.inc new file mode 100644 index 0000000000..d9a8d18d0d --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/Makefile.inc @@ -0,0 +1,5 @@ +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += bootblock.c diff --git a/src/mainboard/asrock/b85m_pro4/acpi/ec.asl b/src/mainboard/asrock/b85m_pro4/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/asrock/b85m_pro4/acpi/platform.asl b/src/mainboard/asrock/b85m_pro4/acpi/platform.asl new file mode 100644 index 0000000000..c70c466720 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/acpi/platform.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PTS, 1) +{ +} + +Method(_WAK, 1) +{ + Return(Package(){0, 0}) +} diff --git a/src/mainboard/asrock/b85m_pro4/acpi/superio.asl b/src/mainboard/asrock/b85m_pro4/acpi/superio.asl new file mode 100644 index 0000000000..b671e3cb37 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/acpi/superio.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define NCT6776_SHOW_PP +#define NCT6776_SHOW_SP1 +#define NCT6776_SHOW_KBC +#define NCT6776_SHOW_HWM + +#undef NCT6776_SHOW_GPIO + +#include diff --git a/src/mainboard/asrock/b85m_pro4/acpi_tables.c b/src/mainboard/asrock/b85m_pro4/acpi_tables.c new file mode 100644 index 0000000000..10e5f944ba --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/acpi_tables.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/asrock/b85m_pro4/board_info.txt b/src/mainboard/asrock/b85m_pro4/board_info.txt new file mode 100644 index 0000000000..a9a29cb009 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/B85M%20Pro4/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/asrock/b85m_pro4/bootblock.c b/src/mainboard/asrock/b85m_pro4/bootblock.c new file mode 100644 index 0000000000..6a66121aa6 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/bootblock.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2018 Tristan Corrick + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select HWM/LED functions instead of floppy functions */ + pnp_write_config(GLOBAL_DEV, 0x1c, 0x03); + pnp_write_config(GLOBAL_DEV, 0x24, 0x24); + + /* Power RAM in S3 and let the PCH handle power failure actions */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default new file mode 100644 index 0000000000..c51001c03c --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Debug +nmi=Enable +power_on_after_fail=Disable diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout new file mode 100644 index 0000000000..f9236e10a8 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/cmos.layout @@ -0,0 +1,65 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- + entries +# ----------------------------------------------------------------- +# Offset Size Type Enum Name +# ----------------------------------------------------------------- + 0 120 r 0 reserved_memory + 384 1 e 3 boot_option + 388 4 h 0 reboot_counter + 395 4 e 4 debug_level + 408 1 e 1 nmi + 409 2 e 5 power_on_after_fail + 984 16 h 0 check_sum +# ----------------------------------------------------------------- + + +# ----------------------------------------------------------------- + enumerations +# ----------------------------------------------------------------- +# ID Value Text +# ----------------------------------------------------------------- + 1 0 Disable + 1 1 Enable +# ----------------------------------------------------------------- + 3 0 Fallback + 3 1 Normal +# ----------------------------------------------------------------- + 4 0 Emergency + 4 1 Alert + 4 2 Critical + 4 3 Error + 4 4 Warning + 4 5 Notice + 4 6 Info + 4 7 Debug + 4 8 Spew +# ----------------------------------------------------------------- + 5 0 Disable + 5 1 Enable + 5 2 Keep +# ----------------------------------------------------------------- + + +# ----------------------------------------------------------------- + checksums +# ----------------------------------------------------------------- +# Start End Store +# ----------------------------------------------------------------- + checksum 392 415 984 +# ----------------------------------------------------------------- diff --git a/src/mainboard/asrock/b85m_pro4/data.vbt b/src/mainboard/asrock/b85m_pro4/data.vbt new file mode 100644 index 0000000000..93b2418f71 Binary files /dev/null and b/src/mainboard/asrock/b85m_pro4/data.vbt differ diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb new file mode 100644 index 0000000000..5cf4cf4cc8 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -0,0 +1,119 @@ +chip northbridge/intel/haswell + + device cpu_cluster 0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + + device lapic 0 on end + device lapic 0xacac off end + end + end + + device domain 0 on + subsystemid 0x1849 0x0c00 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe graphics + device pci 02.0 on end # iGPU + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x80" + register "pirqc_routing" = "0x83" + register "pirqd_routing" = "0x8a" + register "pirqe_routing" = "0x83" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x8b" + register "pirqh_routing" = "0x8a" + register "sata_ahci" = "1" + register "sata_port_map" = "0x3f" + + device pci 14.0 on end # xHCI controller + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 on end # ME KT + device pci 19.0 on end # Intel GbE through I217-V PHY + device pci 1a.0 on end # EHCI #2 + device pci 1b.0 on end # HD Audio + device pci 1c.0 on end # RP #1: ASM1083 PCI bridge + device pci 1c.1 off end # RP #2 + device pci 1c.2 off end # RP #3 + device pci 1c.3 off end # RP #4 + device pci 1c.4 on end # RP #5: PCIe x16 (electrical x4) + device pci 1d.0 on end # EHCI #1 + device pci 1f.0 on # LPC bridge + + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel + io 0x60 = 0x0378 + irq 0x70 = 6 + drq 0x74 = 2 + irq 0xf0 = 0x3b + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 12 # + Keyboard + irq 0x72 = 12 # + Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on # GPIO0 + irq 0xe0 = 0xf9 # + GPIO0 direction + irq 0xe1 = 0xfb # + GPIO0 value + irq 0xf0 = 0xf1 # + GPIO1 direction + irq 0xf1 = 0xf1 # + GPIO1 value + end + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 on end # GPIO1 + device pnp 2e.209 on # GPIO2 + irq 0xe0 = 0xff # + GPIO2 direction + end + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a on # ACPI + irq 0xe0 = 0x41 # + Enable KBC wakeup + irq 0xe4 = 0x10 # + Power RAM in S3 + irq 0xf0 = 0x20 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 + io 0x60 = 0x0290 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asrock/b85m_pro4/dsdt.asl b/src/mainboard/asrock/b85m_pro4/dsdt.asl new file mode 100644 index 0000000000..0fa3253a43 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/dsdt.asl @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Angel Pons + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include "acpi/superio.asl" + #include + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + #include + } +} diff --git a/src/mainboard/asrock/b85m_pro4/gma-mainboard.ads b/src/mainboard/asrock/b85m_pro4/gma-mainboard.ads new file mode 100644 index 0000000000..c595ad4c84 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/gma-mainboard.ads @@ -0,0 +1,30 @@ +-- +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2018 Angel Pons +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; version 2 of the License. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- DVI-D + HDMI3, -- HDMI + Analog, -- VGA + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/b85m_pro4/gpio.c b/src/mainboard/asrock/b85m_pro4/gpio.c new file mode 100644 index 0000000000..4400451568 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/gpio.c @@ -0,0 +1,196 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/b85m_pro4/hda_verb.c b/src/mainboard/asrock/b85m_pro4/hda_verb.c new file mode 100644 index 0000000000..bc7c0292c9 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/hda_verb.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek ALC892 */ + 0x1849c892, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1849c892), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014020), + AZALIA_PIN_CFG(0, 0x17, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x02a11c3f), + AZALIA_PIN_CFG(0, 0x1b, 0x01813c30), + AZALIA_PIN_CFG(0, 0x1d, 0x598301f0), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x0221102f), + + 0x10ec0887, /* Codec Vendor / Device ID: Realtek ALC887 */ + 0x1458a002, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(2, 0x1458a002), + AZALIA_PIN_CFG(2, 0x11, 0x411110f0), + AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x14, 0x01014410), + AZALIA_PIN_CFG(2, 0x15, 0x411111f0), + AZALIA_PIN_CFG(2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(2, 0x18, 0x01a19c50), + AZALIA_PIN_CFG(2, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(2, 0x1a, 0x0181345f), + AZALIA_PIN_CFG(2, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1f, 0x41c46060), + + 0x80862806, /* Codec Vendor / Device ID: Intel Haswell HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x58560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c new file mode 100644 index 0000000000..84b0f62992 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2018 Tristan Corrick + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static const struct rcba_config_instruction rcba_config[] = { + RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), + RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), + RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), + RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), + RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)), + RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +void mainboard_romstage_entry(void) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 1, /* desktop/server */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, + .ec_present = 0, + .gbe_enable = 1, + .dimm_channel0_disabled = 0, + .dimm_channel1_disabled = 0, + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + }, + .usb3_ports = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = &rcba_config[0], + }; + + romstage_common(&romstage_params); +} -- cgit v1.2.3