From df5e6f64b6dd465cb6253159dc3c7335e763dbde Mon Sep 17 00:00:00 2001 From: Philipp Hug Date: Wed, 11 Jul 2018 13:31:34 +0200 Subject: soc/sifive/fu540: Implement uart_platform_refclk for UART divisor calculation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After changing clock from 33.33Mhz to 1Ghz the UART divisor needs to be recalculated. Return correct tlck frequency in uart_platform_refclk. Change-Id: I2291e4198cf466a8334211c6c46bc3268fc979a9 Signed-off-by: Philipp Hug Reviewed-on: https://review.coreboot.org/28584 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich Reviewed-by: Jonathan Neuschäfer --- src/soc/sifive/fu540/uart.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/soc/sifive/fu540/uart.c b/src/soc/sifive/fu540/uart.c index c53f42d9d8..b563be13b1 100644 --- a/src/soc/sifive/fu540/uart.c +++ b/src/soc/sifive/fu540/uart.c @@ -13,8 +13,11 @@ * GNU General Public License for more details. */ +#include +#include #include #include +#include uintptr_t uart_platform_base(int idx) { @@ -29,5 +32,9 @@ unsigned int uart_platform_refclk(void) /* * The SiFive UART uses tlclk, which is coreclk/2 as input */ - return 33330000 / 2; + + if (ENV_BOOTBLOCK) + return 33330000 / 2; + else + return clock_get_coreclk_khz() * KHz / 2; } -- cgit v1.2.3