From e9eb14079c22f00342f8f884791e24d82980c2b4 Mon Sep 17 00:00:00 2001 From: Shamile Khan Date: Mon, 9 Apr 2018 16:44:23 -0700 Subject: soc/intel/common/block/gspi: Set Clock Update Bit for clock updates. This is required for clock parameter settings to take effect. BUG=b:75306520 BRANCH=None TEST=On Octopus, used a scope to check that spi_clk fed to tpm is 1 MHz Change-Id: Icdb617aa4aa944d46b3a56dab88d2008b01dea0d Signed-off-by: Shamile Khan Reviewed-on: https://review.coreboot.org/25573 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/common/block/gspi/gspi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index e4e44c22bb..8bf27de1cf 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -465,7 +465,8 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev) * Program m/n divider. * Set m and n to 1, so that this divider acts as a pass-through. */ - clocks = (1 << CLOCKS_N_SHIFT) | (1 << CLOCKS_M_SHIFT) | CLOCKS_ENABLE; + clocks = (1 << CLOCKS_N_SHIFT) | (1 << CLOCKS_M_SHIFT) | CLOCKS_ENABLE | + CLOCKS_UPDATE; gspi_write_mmio_reg(p, CLOCKS, clocks); udelay(10); -- cgit v1.2.3