From f1d807c5c603e9a77cf3ddd54e4aa3ceebcc3ae9 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 21 Mar 2016 02:14:50 -0500 Subject: nb/amd/mct_ddr3: Remove spurious Addl_Index variable in dqsTrainMaxRdLatency_SW_Fam15() Change-Id: Ic3f636983cf6ba2796ee56e2a25b56513a4343c1 Signed-off-by: Timothy Pearson Reviewed-on: https://review.coreboot.org/14148 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src') diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index da71816d6f..9a0d372528 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -1555,7 +1555,6 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { u8 Channel; - u8 Addl_Index = 0; u8 Receiver; u8 _DisableDramECC = 0, _Wrap32Dis = 0, _SSE2 = 0; u32 Errors; @@ -1629,10 +1628,9 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, * This is essentially looping over each DIMM. */ for (; Receiver < 8; Receiver += 2) { - Addl_Index = (Receiver >> 1) * 3 + 0x10; dimm = (Receiver >> 1); - print_debug_dqs("\t\tTrainMaxRdLatency52: index ", Addl_Index, 2); + print_debug_dqs("\t\tTrainMaxRdLatency52: Receiver ", Receiver, 2); if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver)) { continue; -- cgit v1.2.3