From f3ec5ed5559c59a63419f20246751e6f39225ef7 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sat, 2 Sep 2017 17:59:41 -0400 Subject: cpu/intel/slot_1: Increase CAR size to 8KiB Because cpu/intel/car/romstage.c assumes a 8KiB stack size when setting up stack guards, and all Slot 1 compatible CPUs have enough L1 cache available for the increase. Adjust DCACHE_RAM_BASE to match. Boot tested on asus/p2b-ls and asus/p3b-f using a 1400MHz Tualeron. The latter actually requires this patch to boot successfully. Change-Id: I5b440e7be4f3149378db88872872012c92049c20 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/21349 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel --- src/cpu/intel/slot_1/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index a98232e6cc..f535a03bf1 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -28,10 +28,10 @@ config SLOT_SPECIFIC_OPTIONS # dummy config DCACHE_RAM_BASE hex - default 0xcf000 + default 0xce000 config DCACHE_RAM_SIZE hex - default 0x01000 + default 0x02000 endif -- cgit v1.2.3