From f4c4ab9826b521666d5ba887e69a636428ac9eb2 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Thu, 16 Mar 2017 17:08:03 -0700 Subject: soc/intel/skylake: Fix remaining issues detected by checkpatch Fix the following errors and warnings detected by checkpatch.pl: ERROR: code indent should use tabs where possible ERROR: Macros with complex values should be enclosed in parentheses ERROR: "foo * bar" should be "foo *bar" ERROR: space required before the open parenthesis '(' ERROR: spaces required around that '=' (ctx:VxW) WARNING: space prohibited between function name and open parenthesis '(' WARNING: storage class should be at the beginning of the declaration WARNING: char * array declaration might be better as static const WARNING: please, no space before tabs WARNING: braces {} are not necessary for single statement blocks WARNING: else is not generally useful after a break or return WARNING: static const char * array should probably be static const char * const TEST=Build for glados Change-Id: Ic14ca3abd193cfe257504a55ab6b74782b26bf6d Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/18868 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/soc/intel/skylake/acpi.c | 2 +- src/soc/intel/skylake/bootblock/bootblock.c | 2 +- src/soc/intel/skylake/bootblock/pch.c | 2 +- src/soc/intel/skylake/bootblock/report_platform.c | 2 +- src/soc/intel/skylake/chip_fsp20.c | 2 +- src/soc/intel/skylake/cpu.c | 3 +-- src/soc/intel/skylake/include/soc/gpio.h | 2 +- src/soc/intel/skylake/include/soc/p2sb.h | 2 +- src/soc/intel/skylake/me.c | 25 +++++++++++------------ src/soc/intel/skylake/pmutil.c | 12 +++++------ src/soc/intel/skylake/reset.c | 2 +- 11 files changed, 27 insertions(+), 29 deletions(-) (limited to 'src') diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 4f2dafd9fd..d7114349d4 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -568,7 +568,7 @@ void southcluster_inject_dsdt(device_t device) gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) memset(gnvs, 0, sizeof(*gnvs)); } diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index 93a031f0f5..c11d3d2152 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -16,7 +16,7 @@ #include #include -void asmlinkage bootblock_c_entry(uint64_t base_timestamp) +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { /* Call lib/bootblock.c main */ bootblock_main_with_timestamp(base_timestamp); diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 07beae8f9e..62054f14ac 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -123,7 +123,7 @@ static void pch_interrupt_init(void) dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); if (!dev || !dev->chip_info) - return; + return; config = dev->chip_info; pch_interrupt_routing[0] = config->pirqa_routing; diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 12c283fda3..63cd6367ab 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -92,7 +92,7 @@ static void report_cpu_info(void) char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ int vt, txt, aes; msr_t microcode_ver; - const char *mode[] = {"NOT ", ""}; + static const char * const mode[] = {"NOT ", ""}; const char *cpu_type = "Unknown"; index = 0x80000000; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 21d895ecf0..851c957624 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -243,7 +243,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) * Send VR specific mailbox commands: * 000b - no VR specific command sent * 001b - VR mailbox command specifically for the MPS IMPV8 VR - * will be sent + * will be sent * 010b - VR specific command sent for PS4 exit issue * 100b - VR specific command sent for MPS VR decay issue */ diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 447f84a958..0e5d0931cc 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -495,9 +495,8 @@ static void soc_init_cpus(void *unused) assert(dev != NULL); struct bus *cpu_bus = dev->link_list; - if (mp_init_with_smm(cpu_bus, &mp_ops)) { + if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); - } /* Thermal throttle activation offset */ configure_thermal_target(); diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index c0e37db91e..ae534cd9ce 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -97,7 +97,7 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num); PAD_FIELD(GPIOTXDIS, txdis)) #define _PAD_CFG_ATTRS(pad_, term_, dw0_, attrs_) \ - { \ + { \ .pad = pad_, \ .attrs = PAD_FIELD(PAD_TERM, term_) | attrs_, \ .dw0 = dw0_, \ diff --git a/src/soc/intel/skylake/include/soc/p2sb.h b/src/soc/intel/skylake/include/soc/p2sb.h index 354679f2a8..36bb62d675 100644 --- a/src/soc/intel/skylake/include/soc/p2sb.h +++ b/src/soc/intel/skylake/include/soc/p2sb.h @@ -20,7 +20,7 @@ #define HPTC_ADDR_ENABLE_BIT (1 << 7) #define PCH_P2SB_EPMASK0 0xB0 -#define PCH_P2SB_EPMASK(mask_number) PCH_P2SB_EPMASK0 + (mask_number * 4) +#define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + (mask_number * 4)) #define PCH_P2SB_E0 0xE0 #define PCH_PWRM_ACPI_TMR_CTL 0xFC diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index dd734077ce..577437291f 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -49,7 +49,7 @@ static inline void me_write_mmio32(u16 offset, u32 value) } /* HFSTS1[3:0] Current Working State Values */ -static const char *me_cws_values[] = { +static const char * const me_cws_values[] = { [ME_HFS_CWS_RESET] = "Reset", [ME_HFS_CWS_INIT] = "Initializing", [ME_HFS_CWS_REC] = "Recovery", @@ -69,7 +69,7 @@ static const char *me_cws_values[] = { }; /* HFSTS1[8:6] Current Operation State Values */ -static const char *me_opstate_values[] = { +static const char * const me_opstate_values[] = { [ME_HFS_STATE_PREBOOT] = "Preboot", [ME_HFS_STATE_M0_UMA] = "M0 with UMA", [ME_HFS_STATE_M3] = "M3 without UMA", @@ -79,7 +79,7 @@ static const char *me_opstate_values[] = { }; /* HFSTS1[19:16] Current Operation Mode Values */ -static const char *me_opmode_values[] = { +static const char * const me_opmode_values[] = { [ME_HFS_MODE_NORMAL] = "Normal", [ME_HFS_MODE_DEBUG] = "Debug", [ME_HFS_MODE_DIS] = "Soft Temporary Disable", @@ -88,7 +88,7 @@ static const char *me_opmode_values[] = { }; /* HFSTS1[15:12] Error Code Values */ -static const char *me_error_values[] = { +static const char * const me_error_values[] = { [ME_HFS_ERROR_NONE] = "No Error", [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", [ME_HFS_ERROR_IMAGE] = "Image Failure", @@ -96,7 +96,7 @@ static const char *me_error_values[] = { }; /* HFSTS2[31:28] ME Progress Code */ -static const char *me_progress_values[] = { +static const char * const me_progress_values[] = { [ME_HFS2_PHASE_ROM] = "ROM Phase", [1] = "Unknown (1)", [ME_HFS2_PHASE_UKERNEL] = "uKernel Phase", @@ -109,7 +109,7 @@ static const char *me_progress_values[] = { }; /* HFSTS2[27:24] Power Management Event */ -static const char *me_pmevent_values[] = { +static const char * const me_pmevent_values[] = { [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = "Clean Moff->Mx wake", [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = @@ -146,13 +146,13 @@ static const char *me_pmevent_values[] = { }; /* Progress Code 0 states */ -static const char *me_progress_rom_values[] = { +static const char * const me_progress_rom_values[] = { [ME_HFS2_STATE_ROM_BEGIN] = "BEGIN", [ME_HFS2_STATE_ROM_DISABLE] = "DISABLE" }; /* Progress Code 1 states */ -static const char *me_progress_bup_values[] = { +static const char * const me_progress_bup_values[] = { [ME_HFS2_STATE_BUP_INIT] = "Initialization starts", [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = @@ -585,7 +585,7 @@ send_heci_message(void *msg, int len, u8 hostaddress, u8 clientaddress) } static int -recv_heci_message(void *message, u32 * message_size) +recv_heci_message(void *message, u32 *message_size) { union mei_header head; int cur = 0; @@ -652,7 +652,7 @@ static int send_heci_reset_message(void) }; u32 reply_size; - status= send_heci_message(&msg, sizeof(msg), + status = send_heci_message(&msg, sizeof(msg), BIOS_HOST_ADD, HECI_MKHI_ADD); if (status != 0) return -1; @@ -664,10 +664,9 @@ static int send_heci_reset_message(void) if (reply.result != 0) { printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__); return -1; - } else { - printk(BIOS_DEBUG, "%s: Exit with Success\n", __func__); - return 0; } + printk(BIOS_DEBUG, "%s: Exit with Success\n", __func__); + return 0; } int send_global_reset(void) diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 73dc11792c..209bb902e8 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -41,7 +41,7 @@ #include "chip.h" /* Print status bits with descriptive names */ -static void print_status_bits(u32 status, const char *bit_names[]) +static void print_status_bits(u32 status, const char * const bit_names[]) { int i; @@ -109,7 +109,7 @@ static u16 reset_pm1_status(void) /* Print PM1 status bits */ static u16 print_pm1_status(u16 pm1_sts) { - const char *pm1_sts_bits[] = { + static const char * const pm1_sts_bits[] = { [0] = "TMROF", [4] = "BM", [5] = "GBL", @@ -158,7 +158,7 @@ static u32 reset_smi_status(void) /* Print SMI status bits */ static u32 print_smi_status(u32 smi_sts) { - const char *smi_sts_bits[] = { + static const char * const smi_sts_bits[] = { [2] = "BIOS", [3] = "LEGACY_USB", [4] = "SLP_SMI", @@ -245,7 +245,7 @@ static u32 reset_tco_status(void) /* Print TCO status bits */ static u32 print_tco_status(u32 tco_sts) { - const char *tco_sts_bits[] = { + static const char * const tco_sts_bits[] = { [0] = "NMI2SMI", [1] = "SW_TCO", [2] = "TCO_INT", @@ -306,7 +306,7 @@ static u32 reset_gpe(u16 sts_reg, u16 en_reg) } /* Print GPE0 status bits */ -static u32 print_gpe_status(u32 gpe0_sts, const char *bit_names[]) +static u32 print_gpe_status(u32 gpe0_sts, const char * const bit_names[]) { if (!gpe0_sts) return 0; @@ -334,7 +334,7 @@ static u32 print_gpe_gpio(u32 gpe0_sts, int start) /* Clear all GPE status and return "standard" GPE event status */ u32 clear_gpe_status(void) { - const char *gpe0_sts_3_bits[] = { + static const char * const gpe0_sts_3_bits[] = { [1] = "HOTPLUG", [2] = "SWGPE", [6] = "TCO_SCI", diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c index 0994762529..69109145f2 100644 --- a/src/soc/intel/skylake/reset.c +++ b/src/soc/intel/skylake/reset.c @@ -52,7 +52,7 @@ void global_reset(void) void chipset_handle_reset(uint32_t status) { - switch(status) { + switch (status) { case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); global_reset(); -- cgit v1.2.3