From f5cf60f25b8c77e0c90094e3326c5bc0e37cb383 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 18 Mar 2019 15:26:48 +0200 Subject: Move calls to quick_ram_check() before CBMEM init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After raminit completes, do a read-modify-write test just below CBMEM top address. If test fails, die(). Change-Id: I33d4153a5ce0908b8889517394afb46f1ca28f92 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/31978 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Werner Zeh --- src/cpu/intel/haswell/romstage.c | 4 ---- src/include/lib.h | 3 ++- src/lib/imd_cbmem.c | 5 +++++ src/lib/ramtest.c | 10 ++++------ src/mainboard/lenovo/x201/romstage.c | 4 ---- src/mainboard/packardbell/ms2290/romstage.c | 4 ---- src/northbridge/intel/pineview/romstage.c | 3 --- src/northbridge/intel/sandybridge/raminit.c | 4 ---- src/northbridge/intel/x4x/raminit.c | 2 -- src/soc/intel/broadwell/romstage/raminit.c | 4 ---- src/soc/intel/fsp_baytrail/romstage/romstage.c | 7 ------- src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 4 ---- src/southbridge/intel/fsp_rangeley/romstage.c | 4 ---- 13 files changed, 11 insertions(+), 47 deletions(-) (limited to 'src') diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index ee87effc87..0426bb4cea 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -121,9 +120,6 @@ void romstage_common(const struct romstage_params *params) intel_early_me_status(); - quick_ram_check(); - post_code(0x3e); - if (!wake_from_s3) { cbmem_initialize_empty(); /* Save data returned from MRC on non-S3 resumes. */ diff --git a/src/include/lib.h b/src/include/lib.h index 3edc37245e..098d62df52 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -24,10 +24,11 @@ size_t ulzman(const void *src, size_t srcn, void *dst, size_t dstn); /* Defined in src/lib/ramtest.c */ +/* Assumption is 32-bit addressable UC memory. */ void ram_check(unsigned long start, unsigned long stop); int ram_check_nodie(unsigned long start, unsigned long stop); int ram_check_noprint_nodie(unsigned long start, unsigned long stop); -void quick_ram_check(void); +void quick_ram_check_or_die(uintptr_t dst); /* Defined in primitive_memtest.c */ int primitive_memtest(uintptr_t base, uintptr_t size); diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index c458e5e3b1..1a67ad5be1 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -119,6 +120,10 @@ static void cbmem_top_init_once(void) return; cbmem_top_init(); + + /* The test is only effective on X86 and when address hits UC memory. */ + if (ENV_X86) + quick_ram_check_or_die((uintptr_t)cbmem_top() - sizeof(u32)); } void cbmem_initialize_empty_id_size(u32 id, u64 size) diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index eb58c30fe5..489ca28d59 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -171,7 +171,10 @@ int ram_check_noprint_nodie(unsigned long start, unsigned long stop) return failures; } -static void __quick_ram_check(uintptr_t dst) +/* Assumption is 32-bit addressable UC memory at dst. This also executes + * on S3 resume path so target memory must be restored. + */ +void quick_ram_check_or_die(uintptr_t dst) { int fail = 0; u32 backup; @@ -200,8 +203,3 @@ static void __quick_ram_check(uintptr_t dst) } phys_memory_barrier(); } - -void quick_ram_check(void) -{ - __quick_ram_check(0x100000); -} diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index c5a3120838..7e895b46f0 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include @@ -273,7 +272,4 @@ void mainboard_romstage_entry(unsigned long bist) } romstage_handoff_init(s3resume); - - if (!s3resume) - quick_ram_check(); } diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index b20c445fef..35b90f6a2a 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include @@ -266,7 +265,4 @@ void mainboard_romstage_entry(unsigned long bist) } romstage_handoff_init(s3resume); - - if (!s3resume) - quick_ram_check(); } diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index cf1da63f85..e6a344e738 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -18,7 +18,6 @@ */ #include -#include #include #include #include @@ -105,8 +104,6 @@ void mainboard_romstage_entry(unsigned long bist) post_code(0x31); - quick_ram_check(); - mb_pirq_setup(); rcba_config(); diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 3f62d10a1c..4a048db7c7 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -31,7 +31,6 @@ #include #include #include -#include #include "raminit_native.h" #include "raminit_common.h" #include "sandybridge.h" @@ -419,9 +418,6 @@ static void init_dram_ddr3(int min_tck, int s3resume) /* Zone config */ dram_zones(&ctrl, 0); - /* Non intrusive, fast ram check */ - quick_ram_check(); - intel_early_me_status(); intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); intel_early_me_status(); diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 72ef1a915e..02a8b74f70 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -23,7 +23,6 @@ #include #include #include -#include #include "iomap.h" #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #include /* smbus_read_byte */ @@ -734,6 +733,5 @@ void sdram_initialize(int boot_path, const u8 *spd_map) } timestamp_add_now(TS_AFTER_INITRAM); - quick_ram_check(); printk(BIOS_DEBUG, "Memory initialized\n"); } diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 04657aebd8..8d43907f8a 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -98,9 +97,6 @@ void raminit(struct pei_data *pei_data) report_memory_config(); - /* Basic memory sanity test */ - quick_ram_check(); - if (pei_data->boot_mode != ACPI_S3) { cbmem_initialize_empty(); } else if (cbmem_initialize()) { diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index b4eb006aab..c46b09ef97 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include @@ -245,12 +244,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) late_mainboard_romstage_entry(); post_code(0x4c); - /* if S3 resume skip RAM check */ - if (prev_sleep_state != ACPI_S3) { - quick_ram_check(); - post_code(0x4d); - } - cbmem_was_initted = !cbmem_recovery(prev_sleep_state == ACPI_S3); /* Save the HOB pointer in CBMEM to be used in ramstage*/ diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 36e9e6b1db..a75dabd225 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -16,7 +16,6 @@ */ #include -#include #include #include #include @@ -112,9 +111,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) post_code(0x4b); late_mainboard_romstage_entry(); - post_code(0x4c); - quick_ram_check(); - post_code(0x4d); cbmem_was_initted = !cbmem_recovery(0); diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 14611b3891..19e470e309 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include @@ -114,9 +113,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { /* Decode E0000 and F0000 segment to DRAM */ sideband_write(B_UNIT, BMISC, sideband_read(B_UNIT, BMISC) | (1 << 1) | (1 << 0)); - quick_ram_check(); - post_code(0x4d); - cbmem_was_initted = !cbmem_recovery(0); /* Save the HOB pointer in CBMEM to be used in ramstage*/ -- cgit v1.2.3