From f7bcc180eb5aa297aa3e8ff9a3968414a238395a Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Mon, 25 Sep 2017 23:58:39 -0700 Subject: soc/intel/common: Add Cannonlake PCI id MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add extra pci ids of CNLU and CNLY into common code. Change-Id: Ibbf3d500a780cc6a758fda1ddbec2b9953fb5a97 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/21691 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer Reviewed-by: Aaron Durbin Reviewed-by: Sumeet R Pawnikar Reviewed-by: Paul Menzel --- src/soc/intel/common/block/lpc/lpc.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src') diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index da3188d4e6..d42566745d 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -114,6 +114,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM, PCI_DEVICE_ID_INTEL_APL_LPC, PCI_DEVICE_ID_INTEL_GLK_LPC, + PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC, + PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC, PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, 0 }; -- cgit v1.2.3