From fcf7d992bf0e8dfb887b7c1db29852898deb7684 Mon Sep 17 00:00:00 2001
From: Elyes HAOUAS <ehaouas@noos.fr>
Date: Sat, 23 May 2020 09:01:17 +0200
Subject: src: Remove unused 'include <bootmode.h>'

Change-Id: I658023f7c3535a2cddd8e11ca8bebe20ae53ffb0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41670
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/ec/google/chromeec/ec.c                     | 1 -
 src/northbridge/intel/sandybridge/raminit.c     | 1 -
 src/northbridge/intel/sandybridge/raminit_mrc.c | 1 -
 src/soc/cavium/cn81xx/soc.c                     | 1 -
 src/soc/intel/apollolake/romstage.c             | 1 -
 src/soc/intel/broadwell/romstage/romstage.c     | 1 -
 src/soc/intel/skylake/chip.c                    | 1 -
 7 files changed, 7 deletions(-)

(limited to 'src')

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 034e9313c9..233f61bafb 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -3,7 +3,6 @@
 #include <stdint.h>
 #include <string.h>
 #include <assert.h>
-#include <bootmode.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index a2b26ae1bf..72c284fb30 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -2,7 +2,6 @@
 
 #include <console/console.h>
 #include <commonlib/region.h>
-#include <bootmode.h>
 #include <cf9_reset.h>
 #include <string.h>
 #include <arch/cpu.h>
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 43858f53bb..1ec54b328e 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -2,7 +2,6 @@
 
 #include <console/console.h>
 #include <console/usb.h>
-#include <bootmode.h>
 #include <cf9_reset.h>
 #include <string.h>
 #include <device/device.h>
diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c
index 1077824d39..3545d55bd9 100644
--- a/src/soc/cavium/cn81xx/soc.c
+++ b/src/soc/cavium/cn81xx/soc.c
@@ -4,7 +4,6 @@
  * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0.
  */
 
-#include <bootmode.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <soc/addressmap.h>
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 2abeb3a7f6..09537a1af3 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -4,7 +4,6 @@
 #include <device/pci_ops.h>
 #include <arch/symbols.h>
 #include <assert.h>
-#include <bootmode.h>
 #include <cbmem.h>
 #include <cf9_reset.h>
 #include <console/console.h>
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 54d6134b16..3b7aa40049 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -2,7 +2,6 @@
 
 #include <stdint.h>
 #include <arch/romstage.h>
-#include <bootmode.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index b14bb72a7b..a1ef06e6e0 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <bootmode.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <fsp/api.h>
-- 
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