From 8e3464109e47945b1a4d7e3dd0c6e291593de70a Mon Sep 17 00:00:00 2001 From: Indrek Kruusa Date: Thu, 3 Aug 2006 16:48:18 +0000 Subject: Changelog: * src/cpu/amd/model_lx/model_lx_init.c L2 cache initialization removed (moved to northbridge.c) * src/include/cpu/amd/lxdef.h more checked values * src/northbridge/amd/lx/northbridge.c L2 cache initialization added cpubug() commented out * src/northbridge/amd/lx/raminit.c empty function sdram_set_registers() is in use, don't remove * src/mainboard/artecgroup/dbe61/Config.lb irqmap changes * src/mainboard/artecgroup/dbe61/irq_tables.c tentative changes to irq table (currently not in use) * src/mainboard/artecgroup/dbe61/mainboard.c irq assigned manually to NIC * src/mainboard/artecgroup/dbe61/Options.lb gcc 4.0 is OK * targets/artecgroup/dbe61/Config.lb 64K for VSA is OK at moment Signed-off-by: Indrek Kruusa Signed-off-by: Andrei Birjukov git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- targets/artecgroup/dbe61/Config.lb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'targets/artecgroup/dbe61') diff --git a/targets/artecgroup/dbe61/Config.lb b/targets/artecgroup/dbe61/Config.lb index bc56000ec8..1bbe5f1f98 100644 --- a/targets/artecgroup/dbe61/Config.lb +++ b/targets/artecgroup/dbe61/Config.lb @@ -1,11 +1,11 @@ -# Config file for the olpc rev_a +# Config file for the ThinCan dbe61 target dbe61 mainboard artecgroup/dbe61 -# leave 128k for vsa +# leave 64k for vsa option CONFIG_COMPRESSED_ROM_STREAM=0 -option ROM_SIZE=1024*256-128*1024 +option ROM_SIZE=1024*256-64*1024 option FALLBACK_SIZE=ROM_SIZE option DEFAULT_CONSOLE_LOGLEVEL = 11 -- cgit v1.2.3