From f8ee1806ac524bc782c93eccc59ee3c929abddb9 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer <stepan@coresystems.de> Date: Fri, 18 Jan 2008 15:08:58 +0000 Subject: Rename almost all occurences of LinuxBIOS to coreboot. Due to the automatic nature of this update, I am self-acking. It worked in abuild. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- targets/motorola/sandpoint/Config.lb | 6 +++--- targets/motorola/sandpoint/Config.lb.ide_stream | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'targets/motorola') diff --git a/targets/motorola/sandpoint/Config.lb b/targets/motorola/sandpoint/Config.lb index 398fa9e11b..d70562328f 100644 --- a/targets/motorola/sandpoint/Config.lb +++ b/targets/motorola/sandpoint/Config.lb @@ -17,15 +17,15 @@ romimage "normal" ## Exception vectors (other than reset vector) option _EXCEPTION_VECTORS=_RESET+0x100 - ## Start of linuxBIOS in the boot rom + ## Start of coreboot in the boot rom ## = _RESET + exeception vector table size option _ROMSTART=_RESET+0x3100 - ## LinuxBIOS C code runs at this location in RAM + ## Coreboot C code runs at this location in RAM option _RAMBASE=0x00100000 option _RAMSTART=0x00100000 option CONFIG_SANDPOINT_ALTIMUS=1 end -buildrom ./linuxbios.rom ROM_SIZE "normal" +buildrom ./coreboot.rom ROM_SIZE "normal" diff --git a/targets/motorola/sandpoint/Config.lb.ide_stream b/targets/motorola/sandpoint/Config.lb.ide_stream index 85b5c7792a..04b2591584 100644 --- a/targets/motorola/sandpoint/Config.lb.ide_stream +++ b/targets/motorola/sandpoint/Config.lb.ide_stream @@ -74,11 +74,11 @@ romimage "normal" ## Exception vectors (other than reset vector) option _EXCEPTION_VECTORS=_RESET+0x100 - ## Start of linuxBIOS in the boot rom + ## Start of coreboot in the boot rom ## = _RESET + exeception vector table size option _ROMSTART=_RESET+0x3100 - ## LinuxBIOS C code runs at this location in RAM + ## Coreboot C code runs at this location in RAM option _RAMBASE=0x00100000 option _RAMSTART=0x00100000 @@ -87,4 +87,4 @@ romimage "normal" mainboard motorola/sandpoint end -buildrom ./linuxbios.rom ROM_SIZE "normal" +buildrom ./coreboot.rom ROM_SIZE "normal" -- cgit v1.2.3