From 51dde6fe3b2fec59fd42f36fd025ac09910a3764 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 7 Dec 2014 22:11:54 -0700 Subject: inteltool: Start adding Bay Trail - Add silvermont (Bay Trail core) MSRs - these are shared with rangeley/avoton. - Add GPIO values and GPIO muxing information. - Add Bay Trail to the PM list. Still to do: - Northbridge functionality (RCBA, Memory timings, etc.) - Add Graphics registers Change-Id: I9fe0c0f1efe5f4344aeb3bad3f13037555109060 Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/7711 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- util/inteltool/inteltool.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'util/inteltool/inteltool.h') diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 741c509613..1db9e63797 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -152,6 +152,12 @@ /* 82371AB/EB/MB use the same device ID value. */ #define PCI_DEVICE_ID_INTEL_82371XX 0x7110 +/* Bay Trail */ +#define PCI_DEVICE_ID_INTEL_BAYTRAIL 0x0f00 /* SOC Transaction Router */ +#define PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC 0x0f1c +#define PCI_DEVICE_ID_INTEL_BAYTRAIL_GFX 0x0f31 +#define CPUID_BAYTRAIL 0x30670 + /* Intel starts counting these generations with the integration of the DRAM controller */ #define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */ #define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */ -- cgit v1.2.3