From 51dde6fe3b2fec59fd42f36fd025ac09910a3764 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 7 Dec 2014 22:11:54 -0700 Subject: inteltool: Start adding Bay Trail - Add silvermont (Bay Trail core) MSRs - these are shared with rangeley/avoton. - Add GPIO values and GPIO muxing information. - Add Bay Trail to the PM list. Still to do: - Northbridge functionality (RCBA, Memory timings, etc.) - Add Graphics registers Change-Id: I9fe0c0f1efe5f4344aeb3bad3f13037555109060 Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/7711 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- util/inteltool/powermgt.c | 1 + 1 file changed, 1 insertion(+) (limited to 'util/inteltool/powermgt.c') diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 7cdf452b99..579524bd3f 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -705,6 +705,7 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: + case PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC: pmbase = pci_read_word(sb, 0x40) & 0xff80; pm_registers = pch_pm_registers; size = ARRAY_SIZE(pch_pm_registers); -- cgit v1.2.3