From 798564333d541ab29abe210f818a500a7582baf7 Mon Sep 17 00:00:00 2001 From: Maximilian Schander Date: Sun, 5 Nov 2017 06:14:55 +0100 Subject: util/inteltool: Add PCIEXBAR and PXPEPBAR reading for Skylake Both registers behave the same as on the previous generation Taken from * 6th Generation Intel Processor Families for S-Platform Volume 2 of 2 * Page 55 and 62 * 332688-003EN Change-Id: Id02a38a7ab51003c9d0f16ebb2300a16b66a15f9 Signed-off-by: Maximilian Schander Reviewed-on: https://review.coreboot.org/22350 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi Reviewed-by: Nico Huber --- util/inteltool/pcie.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'util/inteltool') diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 53dc4c497e..541d9cadc8 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -263,6 +263,8 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; @@ -484,6 +486,8 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break; -- cgit v1.2.3