From fac95e3bfe7d32ee1b9a89afd8a76c2c41c6b695 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sun, 9 Nov 2014 00:11:28 +0100 Subject: inteltool: add more hardware IDs and PCIEXBAR/PXPEPBAR read support Add IDs of some SNB and Haswell chips; use more descriptive names. Add PCIEXBAR and PXPEPBAR read support for SNB/IVB/Haswell. Change-Id: I16753bf90061fc2065b813b1c2169e7b7bcc89e8 Signed-off-by: Felix Held Reviewed-on: http://review.coreboot.org/7360 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause --- util/inteltool/inteltool.c | 13 ++++++++----- util/inteltool/inteltool.h | 13 ++++++++----- util/inteltool/memory.c | 19 ++++++++++++------- util/inteltool/pcie.c | 32 ++++++++++++++++++++++++++++---- 4 files changed, 56 insertions(+), 21 deletions(-) (limited to 'util/inteltool') diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 2d785477bb..aa251a0022 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -75,11 +75,14 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN, "1st generation (Westmere family) Core Processor" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D, "2nd generation (Sandy Bridge family) Core Processor (Desktop)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M, "2nd generation (Sandy Bridge family) Core Processor (Mobile)" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A, "3rd generation (Ivy Bridge family) Core Processor" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B, "3rd generation (Ivy Bridge family) Core Processor" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C, "3rd generation (Ivy Bridge family) Core Processor" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D, "3rd generation (Ivy Bridge family) Core Processor" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN, "4th generation (Haswell family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3, "2nd generation (Sandy Bridge family) Core Processor (Xeon E3)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D, "3rd generation (Ivy Bridge family) Core Processor (Desktop)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M, "3rd generation (Ivy Bridge family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3, "3rd generation (Ivy Bridge family) Core Processor (Xeon E3 v2)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c, "3rd generation (Ivy Bridge family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D, "4th generation (Haswell family) Core Processor (Desktop)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M, "4th generation (Haswell family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3, "4th generation (Haswell family) Core Processor (Xeon E3 v3)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U, "4th generation (Haswell family) Core Processor ULT" }, /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index e031df316c..741c509613 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -157,11 +157,14 @@ #define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */ #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D 0x0100 /* Sandy Bridge (Desktop) */ #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M 0x0104 /* Sandy Bridge (Mobile) */ -#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A 0x0150 /* Ivy Bridge */ -#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B 0x0154 /* Ivy Bridge */ -#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C 0x0158 /* Ivy Bridge */ -#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D 0x015c /* Ivy Bridge */ -#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN 0x0c04 /* Haswell */ +#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3 0x0108 /* Sandy Bridge (Xeon E3) */ +#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D 0x0150 /* Ivy Bridge (Desktop) */ +#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M 0x0154 /* Ivy Bridge (Mobile) */ +#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3 0x0158 /* Ivy Bridge (Xeon E3 v2) */ +#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c 0x015c /* Ivy Bridge (?) */ +#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D 0x0c00 /* Haswell (Desktop) */ +#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M 0x0c04 /* Haswell (Mobile) */ +#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */ #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */ #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index e2b0ab488c..3aa3e4f73e 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -207,10 +207,14 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) break; case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M: - case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A: /* pretty printing not implemented yet */ - case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B: - case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C: + case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c: + case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: mchbar_phys = pci_read_long(nb, 0x48); mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; @@ -248,12 +252,13 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) printf ("clock_speed_index = %x\n", read_500 (0,0x609, 6) >> 1); dump_timings (); break; - case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A: - case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B: - case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C: - case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c: ivybridge_dump_timings(); break; } diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 549ef4b678..6fa94e9ad8 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -205,6 +205,16 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82X4X: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: + case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c: + case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; @@ -296,12 +306,16 @@ int print_dmibar(struct pci_dev *nb) break; case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3: dmi_registers = sandybridge_dmi_registers; size = ARRAY_SIZE(sandybridge_dmi_registers); - case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A: /* pretty printing not implemented yet */ - case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B: - case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C: - case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: /* pretty printing not implemented yet */ + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c: + case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: dmibar_phys = pci_read_long(nb, 0x68); dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ @@ -393,6 +407,16 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82X4X: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: + case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3: + case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c: + case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; -- cgit v1.2.3