From 3f3f53cd5e05eead7a8b8616244a4665bd14b22b Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Wed, 6 May 2020 11:47:04 -0600 Subject: util/sconfig: Add LPC and ESPI buses Picasso has an LPC and eSPI bridge on the same PCI DEVFN. They can both be active at the same time. This adds a way to specify which devices belong on which bus. i.e., device pci 14.3 on # - D14F3 bridge device espi 0 on chip ec/google/chromeec device pnp 0c09.0 on end end end device lpc 0 on end end BUG=b:154445472 TEST=Built trembyle and saw static.c contained the espi bus. Signed-off-by: Raul E Rangel Change-Id: I0c2f40813c05680f72e5f30cbb13617e8f994841 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41099 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- util/sconfig/sconfig.y | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'util/sconfig/sconfig.y') diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index 597e309a42..161cf81551 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -18,7 +18,7 @@ static struct chip_instance *cur_chip_instance; int number; } -%token CHIP DEVICE REGISTER BOOL STATUS MANDATORY BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO +%token CHIP DEVICE REGISTER BOOL STATUS MANDATORY BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO LPC ESPI %% devtree: { cur_parent = root_parent; } chip; -- cgit v1.2.3