From 8c0702b89b2e71f29f828c54c67f2f6bff89d5c1 Mon Sep 17 00:00:00 2001 From: Carl-Daniel Hailfinger Date: Tue, 18 Nov 2008 00:43:14 +0000 Subject: Currently flashrom assumes every vendor BIOS shares our view about which SPI opcodes should be placed in which location. Move to a less optimistic implementation and actually use the generic SPI read functions. They're useful for abstracting exactly this stuff and that makes them the preferred choice. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- util/flashrom/ichspi.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) (limited to 'util') diff --git a/util/flashrom/ichspi.c b/util/flashrom/ichspi.c index 28ee578ee3..5806ba68d9 100644 --- a/util/flashrom/ichspi.c +++ b/util/flashrom/ichspi.c @@ -300,7 +300,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, if (op.atomic != 0) { /* Select atomic command */ temp16 |= SPIC_ACS; - /* Selct prefix opcode */ + /* Select prefix opcode */ if ((op.atomic - 1) == 1) { /*Select prefix opcode 2 */ temp16 |= SPIC_SPOP; @@ -491,19 +491,15 @@ static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset, for (a = 0; a < page_size; a += maxdata) { if (remaining < maxdata) { - if (run_opcode - (curopcodes->opcode[1], - offset + (page_size - remaining), remaining, - &buf[page_size - remaining]) != 0) { + if (spi_nbyte_read(offset + (page_size - remaining), + &buf[page_size - remaining], remaining)) { printf_debug("Error reading"); return 1; } remaining = 0; } else { - if (run_opcode - (curopcodes->opcode[1], - offset + (page_size - remaining), maxdata, - &buf[page_size - remaining]) != 0) { + if (spi_nbyte_read(offset + (page_size - remaining), + &buf[page_size - remaining], maxdata)) { printf_debug("Error reading"); return 1; } -- cgit v1.2.3