x86 System on a Chip (SoC) Development

SoC development is best done in parallel with development for a specific board. The combined steps are listed here. The development steps for the SoC are listed below:

1. FSP 1.1 required files
2. SoC Required Files
3. Start Booting
4. Early Debug
5. Bootblock
6. TempRamInit

Required Files

Create the directory as src/soc/<Vendor>/<Chip Family>.

The following files are required to build a new SoC:

• Include files
  • include/soc/pei_data.h
  • include/soc/pm.h
• Kconfig - Defines the Kconfig value for the SoC and selects the tool chains for the various stages:
  • select ARCH_BOOTBLOCK_<Tool Chain>
  • select ARCH_RAMSTAGE_<Tool Chain>
  • select ARCH_ROMSTAGE_<Tool Chain>
  • select ARCH_VERSTAGE_<Tool Chain>
• Makefile.inc - Specify the include paths
• memmap.c - Top of usable RAM

Start Booting

Some SoC parts require additional firmware components in the flash. This section describes how to add those pieces.

Intel Firmware Descriptor

The Intel Firmware Descriptor (IFD) is located at the base of the flash part. The following command overwrites the base of the flash image with the Intel Firmware Descriptor:

dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1

Management Engine Binary

Some SoC parts contain and require that the Management Engine (ME) be running before it is possible to bring the x86 processor out of reset. A binary file containing the management engine code must be added to the firmware using the ifdtool. The following commands add this binary blob:

util/ifdtool/ifdtool -i ME:me.bin  build/coreboot.rom
mv build/coreboot.rom.new build/coreboot.rom

Early Debug

Early debugging between the reset vector and the time the serial port is enabled is most easily done by writing values to port 0x80.

Success

When the reset vector is successfully invoked, port 0x80 will output the following value:

• 0x01: POST_RESET_VECTOR_CORRECT - Bootblock successfully executed the reset vector and entered the 16-bit code at _start

Bootblock

Implement the bootblock using the following steps:

1. Create the directory as src/soc/<Vendor>/<Chip Family>/bootblock
2. Add the timestamp.inc file which initializes the floating point registers and saves the initial timestamp.
3. Add the bootblock.c file which:
   1. Enables memory-mapped PCI config access
   2. Updates the microcode by calling intel_update_microcode_from_cbfs
   3. Enable ROM caching
4. Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file
   1. Add the BOOTBLOCK_CPU_INIT value to point to the bootblock.c file
   2. Add the CHIPSET_BOOTBLOCK_INCLUDE value to point to the timestamp.inc file
5. Edit the src/soc/<Vendor>/<Chip Family>/Makefile.inc file
   1. Add the bootblock subdirectory
6. Edit the src/soc/<Vendor>/<Chip Family>/memmap.c file
   1. Add the fsp/memmap.h include file
   2. Add the mmap_region_granularity routine
7. Add the necessary .h files to define the necessary values and structures
8. When successful port 0x80 will output the following values:
   1. 0x01: POST_RESET_VECTOR_CORRECT - Bootblock successfully executed the reset vector and entered the 16-bit code at _start
   2. 0x10: POST_ENTER_PROTECTED_MODE - Bootblock executing in 32-bit mode
   3. 0x10 - Verstage/romstage reached 32-bit mode

Build Note: The following files are included into the default bootblock image:

• src/arch/x86/bootblock_romcc.S added by src/arch/x86/Makefile.inc and includes the following files:
  • src/arch/x86/prologue.inc
  • src/cpu/x86/16bit/reset16.inc
  • src/cpu/x86/16bit/entry16.inc
  • src/cpu/x86/32bit/entry32.inc
  • The code in src/arch/x86/bootblock_romcc.S includes src/soc/<Vendor>/<Chip Family>/bootblock/timestamp.inc using the CONFIG_CHIPSET_BOOTBLOCK_INCLUDE value set above
  • src/cpu/x86/sse_enable.inc
  • The code in src/arch/x86/Makefile.inc invokes the ROMCC tool to convert the following "C" code into assembler as bootblock.inc:
    • src/arch/x86/include/arch/bootblock_romcc.h
    • src/cpu/x86/lapic/boot_cpu.c
    • The CONFIG_BOOTBLOCK_CPU_INIT value set above typically points to the code in src/soc/<Vendor>/<Chip Family>/bootblock/bootblock.c
• src/arch/x86/id.S added by src/arch/x86/Makefile.inc
• src/cpu/intel/fit/fit.S added by src/cpu/intel/fit/Makefile.inc
• src/arch/x86/walkcbfs.S added by src/arch/x86/Makefile.inc

TempRamInit

Enable the call to TempRamInit in two stages:

1. Finding the FSP binary in the read-only CBFS region
2. Call TempRamInit

Find FSP Binary

Use the following steps to locate the FSP binary:

1. Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file
   1. Add "select USE_GENERIC_FSP_CAR_INC" to enable the use of src/drivers/intel/fsp1_1/cache_as_ram.inc
   2. Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common specifically building util.c
2. Debug the result until port 0x80 outputs
   1. 0x90: POST_FSP_TEMP_RAM_INIT - Just before calling TempRamInit
   2. Alternating 0xba and 0x01 - The FSP image was not found
3. Add the FSP binary file to the flash image
4. Set the following Kconfig values:
   • CONFIG_FSP_LOC to the FSP base address specified in the previous step
   • CONFIG_FSP_IMAGE_ID_STRING
5. Debug the result until port 0x80 outputs
   1. 0x90: POST_FSP_TEMP_RAM_INIT - Just before calling TempRamInit
   2. Alternating 0xbb and 0x02 - TempRamInit executed, no CPU microcode update found

Calling TempRamInit

Use the following steps to debug the call to TempRamInit:

1. Add the CPU microcode update file
   1. Add the microcode file with the following command

      util/cbfstool/cbfstool build/coreboot.rom add -t microcode -n cpu_microcode_blob.bin -b <base address> -f cpu_microcode_blob.bin

   2. Set the Kconfig values
      • CONFIG_CPU_MICROCODE_CBFS_LOC set to the value from the previous step
      • CONFIG_CPU_MICROCODE_CBFS_LEN
2. Debug the result until port 0x80 outputs
   1. 0x90: POST_FSP_TEMP_RAM_INIT - Just before calling TempRamInit
   2. 0x2A - Just before calling cache_as_ram_main which is the start of the verstage code which may be part of romstage

Modified: 31 January 2016