## ## SPDX-License-Identifier: GPL-2.0-only ## This file is part of the coreboot project. ## config ARCH_X86 bool select PCI select RELOCATABLE_MODULES # stage selectors for x86 config ARCH_BOOTBLOCK_X86_32 bool select ARCH_X86 config ARCH_VERSTAGE_X86_32 bool select ARCH_X86 config ARCH_ROMSTAGE_X86_32 bool select ARCH_X86 config ARCH_POSTCAR_X86_32 bool default ARCH_ROMSTAGE_X86_32 && POSTCAR_STAGE config ARCH_RAMSTAGE_X86_32 bool select ARCH_X86 # stage selectors for x64 config ARCH_BOOTBLOCK_X86_64 bool select ARCH_X86 config ARCH_VERSTAGE_X86_64 bool select ARCH_X86 config ARCH_ROMSTAGE_X86_64 bool select ARCH_X86 config ARCH_POSTCAR_X86_64 bool default ARCH_ROMSTAGE_X86_64 && POSTCAR_STAGE config ARCH_RAMSTAGE_X86_64 bool select ARCH_X86 if ARCH_X86 config ARCH_X86_64_PGTBL_LOC hex "x86_64 page table location in CBFS" depends on ARCH_BOOTBLOCK_X86_64 default 0xfffea000 help The position where to place pagetables. Needs to be known at compile time. Must not overlap other files in CBFS. config USE_MARCH_586 def_bool n help Allow a platform or processor to select to be compiled using the '-march=i586' option instead of the typical '-march=i686' # This is an SMP option. It relates to starting up APs. # It is usually set in mainboard/*/Kconfig. # TODO: Improve description. config AP_IN_SIPI_WAIT bool default n depends on ARCH_X86 && SMP config X86_RESET_VECTOR hex depends on ARCH_X86 default 0xfffffff0 help Specify the location of the x86 reset vector. In traditional devices this must match the architectural reset vector to produce a bootable image. Nontraditional designs may use this to position the reset vector into its desired location. config RESET_VECTOR_IN_RAM bool depends on ARCH_X86 select NO_XIP_EARLY_STAGES help Select this option if the x86 processor's reset vector is in preinitialized DRAM instead of the traditional 0xfffffff0 location. # Aligns 16bit entry code in bootblock so that hyper-threading CPUs # can boot AP CPUs to enable their shared caches. config SIPI_VECTOR_IN_ROM bool default n depends on ARCH_X86 # Set the rambase for systems that still need it, only 5 chipsets as of # Sep 2018. This value was 0x100000, chosen to match the entry point # of Linux 2.2 in 1999. The new value, 14 MiB, makes a lot more sense # for as long as we need it; with luck, that won't be much longer. # In the long term, both RAMBASE and RAMTOP should be removed. # This value leaves more than 1 MiB which is required for fam10 # and broadwell_de. config RAMBASE hex default 0xe00000 config RAMTOP hex default 0x1000000 depends on ARCH_X86 # Traditionally BIOS region on SPI flash boot media was memory mapped right below # 4G and it was the last region in the IFD. This way translation between CPU # address space to flash address was trivial. However some IFDs on newer SoCs # have BIOS region sandwiched between descriptor and other regions. Turning off # this option enables soc code to provide custom mmap_boot.c which can be used to # implement complex translation. config X86_TOP4G_BOOTMEDIA_MAP bool default y # This is something you almost certainly don't want to mess with. # How many SIPIs do we send when starting up APs and cores? # The answer in 2000 or so was '2'. Nowadays, on many systems, # it is 1. Set a safe default here, and you can override it # on reasonable platforms. config NUM_IPI_STARTS int default 2 config CBMEM_TOP_BACKUP def_bool n help Platform implements non-volatile storage to cache cbmem_top() over stage transitions and optionally also over S3 suspend. config PRERAM_CBMEM_CONSOLE_SIZE hex default 0xc00 help Increase this value if preram cbmem console is getting truncated config PC80_SYSTEM bool default y if ARCH_X86 config BOOTBLOCK_DEBUG_SPINLOOP bool default n help Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait for a JTAG debugger to break into the execution sequence. config HAVE_CMOS_DEFAULT def_bool n depends on HAVE_OPTION_TABLE config CMOS_DEFAULT_FILE string default "src/mainboard/$(MAINBOARDDIR)/cmos.default" depends on HAVE_CMOS_DEFAULT config IOAPIC_INTERRUPTS_ON_FSB bool default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS bool default n config HPET_ADDRESS_OVERRIDE def_bool n config HPET_ADDRESS hex default 0xfed00000 if !HPET_ADDRESS_OVERRIDE config ID_SECTION_OFFSET hex default 0x80 # 64KiB default bootblock size config C_ENV_BOOTBLOCK_SIZE hex default 0x10000 # Default address romstage is to be linked at config ROMSTAGE_ADDR hex default 0x2000000 # Default address verstage is to be linked at config VERSTAGE_ADDR hex default 0x2000000 # Use the post CAR infrastructure for tearing down cache-as-ram # from a program loaded in RAM and subsequently loading ramstage. config POSTCAR_STAGE def_bool y depends on ARCH_X86 depends on !RESET_VECTOR_IN_RAM config VERSTAGE_DEBUG_SPINLOOP bool default n help Add a spin (JMP .) in assembly_entry.S during early verstage to wait for a JTAG debugger to break into the execution sequence. config ROMSTAGE_DEBUG_SPINLOOP bool default n help Add a spin (JMP .) in assembly_entry.S during early romstage to wait for a JTAG debugger to break into the execution sequence. choice prompt "Bootblock behaviour" default BOOTBLOCK_SIMPLE depends on !VBOOT config BOOTBLOCK_SIMPLE bool "Always load fallback" config BOOTBLOCK_NORMAL select CONFIGURABLE_CBFS_PREFIX bool "Switch to normal if CMOS says so" endchoice config SKIP_MAX_REBOOT_CNT_CLEAR bool "Do not clear reboot count after successful boot" depends on BOOTBLOCK_NORMAL help Do not clear the reboot count immediately after successful boot. Set to allow the payload to control normal/fallback image recovery. Note that it is the responsibility of the payload to reset the normal boot bit to 1 after each successful boot. config ACPI_BERT bool depends on HAVE_ACPI_TABLES help Build an ACPI Boot Error Record Table. config COLLECT_TIMESTAMPS_NO_TSC bool default n depends on COLLECT_TIMESTAMPS help Use a non-TSC platform-dependent source for timestamps. config COLLECT_TIMESTAMPS_TSC bool default y if !COLLECT_TIMESTAMPS_NO_TSC default n depends on COLLECT_TIMESTAMPS help Use the TSC as the timestamp source. config PAGING_IN_CACHE_AS_RAM bool default n depends on ARCH_X86 help Chipsets scan select this option to preallocate area in cache-as-ram for storing paging data structures. PAE paging is currently the only thing being supported. config NUM_CAR_PAGE_TABLE_PAGES int default 5 depends on PAGING_IN_CACHE_AS_RAM help The number of 4KiB pages that should be pre-allocated for page tables. # Provide the interrupt handlers to every stage. Not all # stages may take advantage. config IDT_IN_EVERY_STAGE bool default n depends on ARCH_X86 config HAVE_CF9_RESET bool config HAVE_CF9_RESET_PREPARE bool depends on HAVE_CF9_RESET config PIRQ_ROUTE bool default n config MAX_PIRQ_LINKS int default 4 depends on PIRQ_ROUTE help This variable specifies the number of PIRQ interrupt links which are routable. On most chipsets, this is 4, INTA through INTD. Some chipsets offer more than four links, commonly up to INTH. They may also have a separate link for ATA or IOAPIC interrupts. When the PIRQ table specifies links greater than 4, pirq_route_irqs will not function properly, unless this variable is correctly set. config MAX_ACPI_TABLE_SIZE_KB int default 144 help Set the maximum size of all ACPI tables in KiB. endif