/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H

#include <soc/gpe.h>
#include <soc/gpio.h>

#ifndef __ACPI__

/* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = {
/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0),
/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00),
/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00),
/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00),
/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00),
/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0),
/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_A7, 0x44000201, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_A8, 0x44000300, 0x3000),
/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000),
/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000),
/* GPIO */_PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_A12, 0x4000200, 0x0),
/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0),
/* SUS_STAT# */_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0),
/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x3000),
/* CLKOUT_48 */_PAD_CFG_STRUCT(GPP_A16, 0x44000500, 0x0),
/* ISH_GP7 */_PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_A18, 0x44000300, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_A19, 0x44000300, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x1000),
/* n/a */_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0),
/* n/a */_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_B3, 0x84000102, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0),
/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0),
/* SRCCLKREQ1# */_PAD_CFG_STRUCT(GPP_B6, 0x44000700, 0x0),
/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x0),
/* SRCCLKREQ3# */_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x0),
/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_B10, 0x44000102, 0x0),
/* n/a */_PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0),
/* SLP_S0# */_PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0),
/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000),
/* GPIO */_PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_B16, 0x84800102, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_B17, 0x84800102, 0x3000),
/* GPIO */_PAD_CFG_STRUCT(GPP_B18, 0x84800102, 0x3000),
/* GPIO */_PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x0),
/* GSPI1_CLK */_PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000),
/* GSPI1_MISO */_PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000),
/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000),
/* GPIO */_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000),
/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0),
/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000),
/* GPIO */_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000),
/* SML0CLK */_PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x3000),
/* SML0DATA */_PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x3000),
/* GPIO */_PAD_CFG_STRUCT(GPP_C5, 0x44800100, 0x1000),
/* RESERVED */_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00),
/* RESERVED */_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00),
/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x3000),
/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0),
/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0),
/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, 0x44000702, 0x0),
/* UART1_RXD */_PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0),
/* UART1_TXD */_PAD_CFG_STRUCT(GPP_C13, 0x44000700, 0x0),
/* UART1_RTS# */_PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0),
/* UART1_CTS# */_PAD_CFG_STRUCT(GPP_C15, 0x44000702, 0x0),
/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x3000),
/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x3000),
/* I2C1_SDA */_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x3000),
/* I2C1_SCL */_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x3000),
/* UART2_RXD */_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x3000),
/* UART2_TXD */_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0),
/* UART2_RTS# */_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0),
/* UART2_CTS# */_PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0),
/* n/a */_PAD_CFG_STRUCT(GPP_D0, 0x44000700, 0x0),
/* n/a */_PAD_CFG_STRUCT(GPP_D1, 0x44000700, 0x0),
/* n/a */_PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0),
/* n/a */_PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0),
/* ISH_I2C2_SDA */_PAD_CFG_STRUCT(GPP_D4, 0x44000700, 0x0),
/* I2S_SFRM */_PAD_CFG_STRUCT(GPP_D5, 0x44000702, 0x3000),
/* I2S_TXD */_PAD_CFG_STRUCT(GPP_D6, 0x44000702, 0x3000),
/* I2S_RXD */_PAD_CFG_STRUCT(GPP_D7, 0x44000702, 0x3000),
/* I2S_SCLK */_PAD_CFG_STRUCT(GPP_D8, 0x44000702, 0x3000),
/* GPIO */_PAD_CFG_STRUCT(GPP_D9, 0x44000102, 0x3000),
/* GPIO */_PAD_CFG_STRUCT(GPP_D10, 0x44000102, 0x3000),
/* GPIO */_PAD_CFG_STRUCT(GPP_D11, 0x44000102, 0x3000),
/* GPIO */_PAD_CFG_STRUCT(GPP_D12, 0x44000102, 0x3000),
/* ISH_UART0_RXD */_PAD_CFG_STRUCT(GPP_D13, 0x44000702, 0x3000),
/* ISH_UART0_TXD */_PAD_CFG_STRUCT(GPP_D14, 0x44000700, 0x3000),
/* ISH_UART0_RTS# */_PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0),
/* ISH_UART0_CTS# */_PAD_CFG_STRUCT(GPP_D16, 0x44000702, 0x0),
/* DMIC_CLK1 */_PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0),
/* DMIC_DATA1 */_PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x1000),
/* DMIC_CLK0 */_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0),
/* DMIC_DATA0 */_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x1000),
/* n/a */_PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0),
/* n/a */_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0),
/* ISH_I2C2_SCL */_PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_E0, 0x44000200, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_E1, 0x44800102, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_E3, 0x44000103, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x0),
/* SATA_DEVSLP1 */_PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0),
/* SATA_DEVSLP2 */_PAD_CFG_STRUCT(GPP_E6, 0x4000700, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x0),
/* SATA_LED# */_PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0),
/* USB_OC0# */_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0),
/* USB_OC1# */_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0),
/* USB_OC2# */_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x0),
/* n/a */_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0),
/* n/a */_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_E15, 0x80880102, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_E16, 0x84000102, 0x0),
/* n/a */_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0),
/* n/a */_PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x3000),
/* n/a */_PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000),
/* n/a */_PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x3000),
/* n/a */_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000),
/* GPIO */_PAD_CFG_STRUCT(GPP_E22, 0x44000000, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000),
/* BATLOW# */_PAD_CFG_STRUCT(GPD0, 0x4000702, 0x3000),
/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, 0x4000702, 0x0),
/* LAN_WAKE# */_PAD_CFG_STRUCT(GPD2, 0x4000602, 0x3c00),
/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000),
/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0),
/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0),
/* SLP_A# */_PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0),
/* SUSCLK */_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0),
/* SLP_WLAN# */_PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0),
/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0),
/* LANPHYPC */_PAD_CFG_STRUCT(GPD11, 0x4000700, 0x0),
/* SATAXPCIE3 */_PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0),
/* SATAXPCIE4 */_PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0),
/* SATAXPCIE5 */_PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0),
/* SATAXPCIE6 */_PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0),
/* SATAXPCIE7 */_PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2003000),
/* SATA_DEVSLP3 */_PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2003000),
/* SATA_DEVSLP4 */_PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2003000),
/* SATA_DEVSLP5 */_PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2003000),
/* SATA_DEVSLP6 */_PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2003000),
/* SATA_DEVSLP7 */_PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2003000),
/* n/a */_PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2003000),
/* n/a */_PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2003000),
/* SATA_SDATAOUT1 */_PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0),
/* SATA_SDATAOUT2 */_PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x0),
/* n/a */_PAD_CFG_STRUCT(GPP_F14, 0x44000700, 0x0),
/* USB_OC4# */_PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x0),
/* USB_OC5# */_PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0),
/* USB_OC6# */_PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0),
/* USB_OC7# */_PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0),
/* eDP_VDDEN */_PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0),
/* eDP_BKLTEN */_PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0),
/* eDP_BKLTCTL */_PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0),
/* n/a */_PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0),
/* GPIO */_PAD_CFG_STRUCT(GPP_F23, 0x44000102, 0x0),
/* FAN_TACH_0 */_PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0),
/* FAN_TACH_1 */_PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0),
/* FAN_TACH_2 */_PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0),
/* FAN_TACH_3 */_PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0),
/* FAN_TACH_4 */_PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0),
/* FAN_TACH_5 */_PAD_CFG_STRUCT(GPP_G5, 0x44000702, 0x0),
/* FAN_TACH_6 */_PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0),
/* FAN_TACH_7 */_PAD_CFG_STRUCT(GPP_G7, 0x44000700, 0x1000),
};

#endif

#endif