##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
	default ROM_SECTION_SIZE   = FALLBACK_SIZE
	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
else
	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
	default ROM_SECTION_OFFSET = 0
end

##
## Compute the start location and size size of
## The linuxBIOS bootloader.
##
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )

##
## Compute where this copy of linuxBIOS will start in the boot rom
##
default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )

##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
default XIP_ROM_SIZE=65536
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )

##
## Set all of the defaults for an x86 architecture
##

arch i386 end

##
## Build the objects we have code for in this directory.
##

driver mainboard.o

if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o

##
## Romcc output
##
makerule ./failover.E
	depends "$(MAINBOARD)/failover.c ./romcc" 
	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end

makerule ./failover.inc
	depends "$(MAINBOARD)/failover.c ./romcc"
	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end

makerule ./auto.E 
	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
	action	"./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc 
	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
	action	"./romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end

##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds

##
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE 
	mainboardinit cpu/x86/16bit/reset16.inc 
	ldscript /cpu/x86/16bit/reset16.lds 
else
	mainboardinit cpu/x86/32bit/reset32.inc 
	ldscript /cpu/x86/32bit/reset32.lds 
end

### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc

##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds

###
### This is the early phase of linuxBIOS startup 
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
	ldscript /arch/i386/lib/failover.lds 
	mainboardinit ./failover.inc
end

###
### O.k. We aren't just an intermediary anymore!
###

##
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit ./auto.inc

##
## Include the secondary Configuration files 
##
dir /pc80
config chip.h

chip northbridge/amd/lx
	register "irqmap" = "0xcba5"
	device apic_cluster 0 on
		chip cpu/amd/model_lx
			device apic 0 on end
		end
	end
  	device pci_domain 0 on 

 		device pci 1.0 on end	# Host Bridge
 
# 		chip drivers/pci/realmode
# 			device pci 1.1 on end  					# VGA
# 			register "rom_address" = "0xfffc0000"	# at the beginning of 256k
# 		end
 		
 		device pci 1.2 off end	# AES
     		chip southbridge/amd/cs5536_lx
 			register "enable_ide_nand_flash" = "0"
 
 			register "isa_irq" = "0"
 			#register "flash_irq" = "14"
 
 			## IDE IRQ
 			register "enable_ide_irq" = "0"
 
 			register "audio_irq" = "5"
 			register "usb_irq" = "7"
 			
 			register "uart0_irq" = "0"
 			register "uart1_irq" = "4"
 
 			## PCI INTA ... INTD and their GPIO pins
 			##   int==0: disable 
 			register "pci_int[0]" = "0"
 			register "pci_int[1]" = "10"
 			register "pci_int[2]" = "0"
 			register "pci_int[3]" = "0"
 			register "pci_int_pin[0]" = "0"
 			register "pci_int_pin[1]" = "7"
 			register "pci_int_pin[2]" = "0"
 			register "pci_int_pin[3]" = "0"									
 
 
 			# Keyboard Emulation Logic IRQs
 			# Enable keyboard IRQ2
 			register "enable_kel_keyb_irq" = "0"
 			# Enable mouse IRQ12
 			register "enable_kel_mouse_irq" = "0"
 			# Configure KEL Emulation IRQ, 0 to disable
 			register "kel_emul_irq" = "0"
 
       		device pci f.0 on end	# ISA Bridge
			device pci f.1 on end	# Flash controller
 			device pci f.2 off end	# IDE controller
       		device pci f.3 on end 	# Audio
        		device pci f.4 on end	# OHCI
			device pci f.5 on end	# EHCI
 			device pci f.6 off end	# UDC controller
 			device pci f.7 off end	# OTG controller
 		end
# 		chip drivers/pci/rtl8139
## 			device pci d.0 on end	# Realtek LAN
# 			register "nic_irq" = "10"
#        		end
   	end
end