# This file is part of the coreboot project.
# SPDX-License-Identifier: GPL-2.0-or-later

chip northbridge/intel/x4x		# Northbridge
	device domain 0 on		# PCI domain
		subsystemid 0x1043 0x8179 inherit
		chip southbridge/intel/i82801gx	# Southbridge
			device pci 1f.0 on		# ISA bridge
				chip superio/winbond/w83627dhg
					device pnp 2e.0 off end		# Floppy
					device pnp 2e.1 on		# Parallel port
						io 0x60 = 0x378
						irq 0x70 = 7
						drq 0x74 = 3
					end
					device pnp 2e.2 on		# COM1
						io 0x60 = 0x3f8
						irq 0x70 = 4
					end
					device pnp 2e.3 off end		# COM2, IR
					device pnp 2e.5 on		# Keyboard, mouse
						io 0x60 = 0x60
						io 0x62 = 0x64
						irq 0x70 = 1
						irq 0x72 = 12
					end
					device pnp 2e.6 off end		# SPI
					device pnp 2e.7 on  end		# GPIO6 (all input)
					device pnp 2e.8 off end		# WDT0#, PLED
					device pnp 2e.9 on		# GPIO2
						irq 0xe4 = 0x04
					end
					device pnp 2e.109 off end	# GPIO3
					device pnp 2e.209 on		# GPIO4
						irq 0xe8 = 0x80
					end
					device pnp 2e.309 on		# GPIO5
						irq 0xfa = 0xff
						irq 0xf3 = 0x09 # RSVD SUSLED settings
					end
					device pnp 2e.a on		# ACPI
						irq 0xe4 = 0x10 # Power dram during s3
						irq 0xe6 = 0x8c
						irq 0xf2 = 0x7d
					end
					device pnp 2e.b on		# HWM, front panel LED
						io 0x60 = 0x290
						irq 0x70 = 0
						irq 0xf1 = 0xff
						irq 0xf2 = 0x83
					end
					device pnp 2e.c on		# PECI, SST
						irq 0xe0 = 0x10
						irq 0xe1 = 0x64
						irq 0xe8 = 0x01
					end
				end
			end
		end
	end
end