# This file is part of the coreboot project. # SPDX-License-Identifier: GPL-2.0-only # Memory chip: Hynix H5TQ4G63MFR-PBC with ECC # BAP ODE E20XX has 2GB RAM soldered down on the Q7 # Memory setting for DDR-1066 # 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage # bits[3:0]: 1 = 128 SPD Bytes Used # bits[6:4]: 1 = 256 SPD Bytes Total # bit7 : 0 = CRC covers bytes 0 ~ 125 11 # 1 SPD Revision - # 0x12 = Revision 1.2 12 # 2 Key Byte / DRAM Device Type # bits[7:0]: 0x0b = DDR3 SDRAM 0B # 3 Key Byte / Module Type # bits[3:0]: 3 = SO-DIMM # bits[7:4]: reserved 03 # 4 SDRAM CHIP Density and Banks # bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip # bits[6:4]: 0 = 3 (8 banks) # bit7 : reserved 04 # 5 SDRAM Addressing # bits[2:0]: 1 = 10 Column Address Bits # bits[5:3]: 3 = 15 Row Address Bits # bits[7:6]: reserved 19 # 6 Module Nominal Voltage, VDD # bit0 : 0 = 1.5 V operable # bit1 : 0 = NOT 1.35 V operable # bit2 : 0 = NOT 1.25 V operable # bits[7:3]: reserved 00 # 7 Module Organization # bits[2:0]: 2 = 16 bits # bits[5:3]: 0 = 1 Rank # bits[7:6]: reserved 02 # 8 Module Memory Bus Width # bits[2:0]: 3 = Primary bus width is 64 bits # bits[4:3]: 1 = 1 bit (bus width extension ECC) # bits[7:5]: reserved 0B # 9 Fine Timebase (FTB) Dividend / Divisor # bits[3:0]: 0x01 divisor # bits[7:4]: 0x01 dividend # 1/1 = 1ps 11 # 10 Medium Timebase (MTB) Dividend # 11 Medium Timebase (MTB) Divisor # 1 / 8 = .125 ns - used for DDR3 01 08 # 12 SDRAM Minimum Cycle Time (tCKmin) # 0x0F = tCKmin of 1.875 ns = DDR3-1066 (533 MHz clock) 0F # 13 Reserved 00 # 14 CAS Latencies Supported, Least Significant Byte # 15 CAS Latencies Supported, Most Significant Byte # Cas Latencies of 8 - 5 are supported 1E 00 # 16 Minimum CAS Latency Time (tAAmin) # 0x69 = 13.125ns - DDR3-1066F 69 # 17 Minimum Write Recovery Time (tWRmin) # 0x78 = tWR of 15ns - All DDR3 speed grades 78 # 18 Minimum RAS# to CAS# Delay Time (tRCDmin) # 0x69 = 13.125ns - DDR3-1066F 69 # 19 Minimum Row Active to Row Active Delay Time (tRRDmin) # 0x3C = 7.5ns 3C # 20 Minimum Row Precharge Delay Time (tRPmin) # 0x69 = 13.125ns - DDR3-1066F 69 # 21 Upper Nibbles for tRAS and tRC # bits[3:0]: tRAS most significant nibble = 1 (see byte 22) # bits[7:4]: tRC most significant nibble = 1 (see byte 23) 11 # 22 Minimum Active to Precharge Delay Time (tRASmin), LSB # 0x12C = 37.5ns - DDR3-1066 (see byte 21) 2C # 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB # 0x195 = 50.625ns - DDR3-1066F (see byte 21) 95 # 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB # 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB # 0x500 = 160ns - for 2 Gigabit chips 80 07 # 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) # 0x3c = 7.5 ns - All DDR3 SDRAM speed bins 3C # 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) # 0x3c = 7.5ns - All DDR3 SDRAM speed bins 3C # 28 Upper Nibble for tFAWmin # 29 Minimum Four Activate Window Delay Time (tFAWmin) # 0x0190 = 50ns - DDR3-1066, 2 KB page size 01 90 # 30 SDRAM Optional Feature # bit0 : 1= RZQ/6 supported # bit1 : 1 = RZQ/7 supported # bits[6:2]: reserved # bit7 : 0 = DLL Off mode supported 03 # 31 SDRAM Thermal and Refresh Options # bit0 : 0 = Temp up to 95c supported # bit1 : 0 = 85-95c uses 2x refresh rate # bit2 : 1 = Auto Self Refresh supported # bit3 : 0 = no on die thermal sensor # bits[6:4]: reserved # bit7 : 0 = partial self refresh supported 04 # 32 Module Thermal Sensor # 0 = Thermal sensor not incorporated onto this assembly 00 # 33 SDRAM Device Type # bits[1:0]: 0 = Signal Loading not specified # bits[3:2]: reserved # bits[6:4]: 0 = Die count not specified # bit7 : 0 = Standard Monolithic DRAM Device 00 # 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) # 35 Fine Offset for Minimum CAS Latency Time (tAAmin) # 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) # 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) # 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) 00 00 00 00 00 # 39 - 59 (reserved) 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # 60 Raw Card Extension, Module Nominal Height # bits[4:0]: 0 = <= 15mm tall # bits[7:5]: 0 = raw card revision 0-3 00 # 61 Module Maximum Thickness # bits[3:0]: 0 = thickness front <= 1mm # bits[7:4]: 0 = thinkness back <= 1mm 00 # 62 Reference Raw Card Used # bits[4:0]: 0 = Reference Raw card A used # bits[6:5]: 0 = revision 0 # bit7 : 0 = Reference raw cards A through AL 00 # 63 Address Mapping from Edge Connector to DRAM # bit0 : 0 = standard mapping (not mirrored) # bits[7:1]: reserved 00 # 64 - 116 (reserved) 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 # 117 - 118 Module ID: Module Manufacturers JEDEC ID Code # 0x80AD = Hynix 80 AD # 119 Module ID: Module Manufacturing Location - oem specified # 120 Module ID: Module Manufacture Year in BCD # 0x00 = 2000 00 00 # 121 Module ID: Module Manufacture week # 0x00 = 0th week 00 # 122 - 125: Module Serial Number 00 00 00 00 # 126 - 127: Cyclical Redundancy Code E9 40