##
## Config file for the Embedded Planet EP405PC Computing Engine
##

uses CONFIG_PCIC0_CFGADDR 
uses CONFIG_CBFS
uses CONFIG_ARCH_X86
uses CONFIG_PCIC0_CFGDATA 
uses CONFIG_ISA_IO_BASE 
uses CONFIG_ISA_MEM_BASE 
uses CONFIG_TTYS0_BASE 
uses CONFIG_IO_BASE 

uses CONFIG_CPU_OPT
uses CONFIG_CROSS_COMPILE 
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_COMPRESS 
uses CONFIG_CHIP_CONFIGURE
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_USE_INIT
uses CONFIG_CONSOLE_SERIAL8250 
uses CONFIG_TTYS0_BAUD CONFIG_TTYS0_DIV
uses CONFIG_NO_POST
uses CONFIG_IDE
uses CONFIG_FS_PAYLOAD
uses CONFIG_FS_EXT2
uses CONFIG_FS_ISO9660
uses CONFIG_FS_FAT
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses CONFIG_AUTOBOOT_CMDLINE
uses CONFIG_SYS_CLK_FREQ
uses CONFIG_IDE_BOOT_DRIVE
#uses CONFIG_IDE_SWAB
uses CONFIG_IDE_OFFSET 
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_RESET
uses CONFIG_EXCEPTION_VECTORS
uses CONFIG_ROMBASE
uses CONFIG_ROMSTART
uses CONFIG_RAMBASE
#uses CONFIG_RAMSTART
uses CONFIG_EMBEDDED_RAM_SIZE
uses CONFIG_STACK_SIZE CONFIG_HEAP_SIZE

uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses CONFIG_CROSS_COMPILE
uses CC
uses CONFIG_HOSTCC
uses CONFIG_OBJCOPY

##
## Set PCI configuration register addresses
##
default CONFIG_PCIC0_CFGADDR=0xeec00000
default CONFIG_PCIC0_CFGDATA=0xeec00004

##
## Set PCI/ISA I/O and memory base address
##
default CONFIG_ISA_IO_BASE=0xe8000000
default CONFIG_ISA_MEM_BASE=0x80000000
default CONFIG_IO_BASE=CONFIG_ISA_IO_BASE

##
## HACK ALERT: the UART0 registers are not in the PCI I/O address space
## but both IDE and UART use the same routines for I/O (inb/outb). To get 
## around this we set TTYSO_BASE to the difference between the two.
##
default CONFIG_TTYS0_BASE=0xef600300-CONFIG_ISA_IO_BASE

## Enable PPC405 instructions
default CONFIG_CPU_OPT="-mcpu=405"
#default CONFIG_CPU_OPT=""
default CONFIG_ARCH_X86=0

## Use stage 1 initialization code
default CONFIG_USE_INIT=1

## Use chip configuration
default CONFIG_CHIP_CONFIGURE=1

## We don't use compressed image
default CONFIG_COMPRESS=0

## Turn off POST codes
default CONFIG_NO_POST=1

## Enable serial console
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
default CONFIG_CONSOLE_SERIAL8250=1
# Divisor of 69 == 9600 baud due to weird clocking
default CONFIG_TTYS0_DIV=69
default CONFIG_TTYS0_BAUD=9600

## Boot linux from IDE
default CONFIG_IDE=1
default CONFIG_FS_PAYLOAD=1
default CONFIG_FS_EXT2=1
default CONFIG_FS_ISO9660=1
default CONFIG_FS_FAT=1
default CONFIG_AUTOBOOT_CMDLINE="hda1:/vmlinuz"

default CONFIG_ROM_SIZE=1048576

## Board has fixed size RAM
default CONFIG_EMBEDDED_RAM_SIZE=64*1024*1024

## Coreboot C code runs at this location in RAM
default CONFIG_RAMBASE=0x00100000

##
## Use a 64K stack
##
default CONFIG_STACK_SIZE=0x10000

##
## Use a 64K heap
##
default CONFIG_HEAP_SIZE=0x10000

##
## System clock
##
default CONFIG_SYS_CLK_FREQ=33

##
default CONFIG_ROMBASE=0xfff00000

## Reset vector address
default CONFIG_RESET=0xfffffffc

## Exception vectors
default CONFIG_EXCEPTION_VECTORS=CONFIG_ROMBASE+0x100

## coreboot ROM start address
default CONFIG_ROMSTART=0xfff03000

## coreboot C code runs at this location in RAM
default CONFIG_RAMBASE=0x00100000

### End Options.lb
#
# CBFS
#
#
default CONFIG_CBFS=0
end