## SPDX-License-Identifier: GPL-2.0-only
## This file is part of the coreboot project.

chip northbridge/intel/sandybridge
	device cpu_cluster 0 on
		chip cpu/intel/model_206ax
			register "c1_acpower" = "1"
			register "c1_battery" = "1"
			register "c2_acpower" = "3"
			register "c2_battery" = "3"
			register "c3_acpower" = "5"
			register "c3_battery" = "5"
			device lapic 0 on	end
			device lapic 0xacac off	end
		end
	end
	register "pci_mmio_size" = "2048"
	device domain 0 on
		subsystemid 0x1458 0x5000 inherit

		device pci 00.0 on end	# Host bridge
		device pci 01.0 on end	# PEG
		device pci 02.0 on end	# iGPU

		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
			register "c2_latency" = "0x0065"
			register "gen1_dec" = "0x003c0a01"
			register "sata_interface_speed_support" = "0x3"
			register "sata_port_map" = "0x33"
			register "spi_lvscc" = "0x2005"
			register "spi_uvscc" = "0x2005"

			device pci 16.0 on  end	# MEI #1
			device pci 1a.0 on  end	# USB2 EHCI #2
			device pci 1b.0 on  end	# HD Audio

			device pci 1d.0 on  end	# USB2 EHCI #1
			device pci 1e.0 off end	# PCI bridge
			device pci 1f.0 on  end	# LPC bridge
			device pci 1f.2 on  end	# SATA Controller 1
			device pci 1f.3 on  end	# SMBus
			device pci 1f.5 off end	# SATA Controller 2
			device pci 1f.6 on  end	# Thermal
		end
	end
end