chip northbridge/amd/amdk8/root_complex # Root complex device lapic_cluster 0 on # (L)APIC cluster chip cpu/amd/socket_AM2 # CPU socket device lapic 0 on end # Local APIC of the CPU end end device domain 0 on # PCI domain subsystemid 0x1022 0x2b80 inherit chip northbridge/amd/amdk8 # Northbridge / RAM controller device pci 18.0 on # Link 0 == LDT 0 chip southbridge/nvidia/mcp55 # Southbridge device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/ite/it8716f # Super I/O device pnp 2e.0 on # Floppy and any LDN # Watchdog from CLKIN (24 MHz) irq 0x23 = 0x11 # Serial Flash (SPI only) # 0x24 = 0x1a io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 2e.1 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.2 off # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end device pnp 2e.3 on # Parallel port io 0x60 = 0x378 irq 0x70 = 7 end device pnp 2e.4 on # Embedded controller io 0x60 = 0x290 io 0x62 = 0x230 irq 0x70 = 9 end device pnp 2e.5 on # PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end device pnp 2e.6 on # PS/2 mouse irq 0x70 = 12 end device pnp 2e.7 on # GPIO, SPI flash # Pin 84 is not GP10 irq 0x25 = 0x0 # Pin 21 is GP26, pin 26 is GP21, pin 27 is GP20 irq 0x26 = 0x43 # Pin 13 is GP35 irq 0x27 = 0x20 # Pin 70 is not GP46 # irq 0x28 = 0x0 # Pin 6,3,128,127,126 is GP63,64,65,66,67 irq 0x29 = 0x81 # Enable FAN_CTL/FAN_TAC set to 5 (pin 21, 23), # enable FAN_CTL/FAN_TAC set to 4 (pin 20, 22), # pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal # voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal # voltage divider for VCC5V # irq 0x2c = 0x1f # Simple I/O base io 0x62 = 0x800 # Serial Flash I/O (SPI only) io 0x64 = 0x820 # Watchdog force timeout (parallel flash only) # irq 0x71 = 0x1 # No WDT interrupt irq 0x72 = 0x0 # GPIO pin set 1 disable internal pullup irq 0xb8 = 0x0 # GPIO pin set 5 enable internal pullup irq 0xbc = 0x01 # SIO pin set 1 alternate function # irq 0xc0 = 0x0 # SIO pin set 2 mixed function irq 0xc1 = 0x43 # SIO pin set 3 mixed function irq 0xc2 = 0x20 # SIO pin set 4 alternate function # irq 0xc3 = 0x0 # SIO pin set 1 input mode # irq 0xc8 = 0x0 # SIO pin set 2 input mode irq 0xc9 = 0x0 # SIO pin set 4 input mode # irq 0xcb = 0x0 # Generate SMI# on EC IRQ # irq 0xf0 = 0x10 # SMI# level trigger # irq 0xf1 = 0x40 # HWMON alert beep pin location irq 0xf6 = 0x28 end device pnp 2e.8 off # MIDI io 0x60 = 0x300 irq 0x70 = 10 end device pnp 2e.9 off # Game port io 0x60 = 0x220 end device pnp 2e.a off end # Consumer IR end end device pci 1.1 on # SM 0 chip drivers/generic/generic # DIMM 0-0-0 device i2c 50 on end end chip drivers/generic/generic # DIMM 0-0-1 device i2c 51 on end end chip drivers/generic/generic # DIMM 0-1-0 device i2c 52 on end end chip drivers/generic/generic # DIMM 0-1-1 device i2c 53 on end end end device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # IDE device pci 5.0 on end # SATA 0 device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on end # PCI device pci 6.1 on end # AUDIO device pci 8.0 on end # NIC device pci 9.0 off end # N/A device pci a.0 on end # PCI E 5 device pci b.0 on end # PCI E 4 device pci c.0 on end # PCI E 3 device pci d.0 on end # PCI E 2 device pci e.0 on end # PCI E 1 device pci f.0 on end # PCI E 0 register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" # 1: SMBus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end end device pci 18.0 on end # Link 1 device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end end # chip drivers/generic/debug # device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all # device pnp 0.2 on end # mem # device pnp 0.3 off end # cpuid # device pnp 0.4 on end # smbus_regs_all # device pnp 0.5 off end # dual core msr # device pnp 0.6 off end # cache size # device pnp 0.7 off end # tsc # device pnp 0.8 off end # io # device pnp 0.9 off end # io # end end