FLASH 16M {
	WP_RO@0x0 0x400000 {
		SI_DESC@0x0 0x1000
		IFWI@0x1000 0x1ff000
		RO_VPD(PRESERVE)@0x200000 0x4000
		RO_SECTION@0x204000 0x1fc000 {
			FMAP@0x0 0x800
			RO_FRID@0x800 0x40
			RO_FRID_PAD@0x840 0x7c0
			COREBOOT(CBFS)@0x1000 0x1f8000
			GBB@0x1f9000 0x3000
		}
	}
	MISC_RW@0x400000 0x30000 {
		RW_PRESERVE(PRESERVE) {
			UNIFIED_MRC_CACHE@0x0 0x21000 {
				RECOVERY_MRC_CACHE@0x0 0x10000
				RW_MRC_CACHE@0x10000 0x10000
				RW_VAR_MRC_CACHE@0x20000 0x1000
			}
		}
		RW_ELOG(PRESERVE)@0x21000 0x3000
		RW_SHARED@0x24000 0x4000 {
			SHARED_DATA@0x0 0x2000
			VBLOCK_DEV@0x2000 0x2000
		}
		RW_VPD(PRESERVE)@0x28000 0x2000
		RW_NVRAM(PRESERVE)@0x2a000 0x5000
		FPF_STATUS@0x2f000 0x1000
	}
	RW_SECTION_A@0x430000 0x480000 {
		VBLOCK_A@0x0 0x10000
		FW_MAIN_A(CBFS)@0x10000 0x46ffc0
		RW_FWID_A@0x47ffc0 0x40
	}
	RW_SECTION_B@0x8b0000 0x480000 {
		VBLOCK_B@0x0 0x10000
		FW_MAIN_B(CBFS)@0x10000 0x46ffc0
		RW_FWID_B@0x47ffc0 0x40
	}
	SMMSTORE(PRESERVE)@0xd30000 0x40000
	RW_LEGACY(CBFS)@0xd70000 0x1c0000
	BIOS_UNUSABLE@0xf30000 0x4f000
	DEVICE_EXTENSION@0xf7f000 0x80000
	# Currently, it is required that the BIOS region be a multiple of 8KiB.
	# This is required so that the recovery mechanism can find SIGN_CSE
	# region aligned to 4K at the center of BIOS region. Since the
	# descriptor at the beginning uses 4K and BIOS starts at an offset of
	# 4K, a hole of 4K is created towards the end of the flash to compensate
	# for the size requirement of BIOS region.
	# FIT tool thus creates descriptor with following regions:
	# Descriptor --> 0 to 4K
	# BIOS       --> 4K to 0xf7f000
	# Device ext --> 0xf7f000 to 0xfff000
	UNUSED_HOLE@0xfff000 0x1000
}