chip soc/intel/cannonlake

	# GPE configuration
	# Note that GPE events called out in ASL code rely on this
	# route. i.e. If this route changes then the affected GPE
	# offset bits also need to be changed.
	register "gpe0_dw0" = "PMC_GPP_A"
	register "gpe0_dw1" = "PMC_GPP_C"
	register "gpe0_dw2" = "PMC_GPP_D"

	# FSP configuration
	register "SaGv" = "3"
	register "HeciEnabled" = "1"
	register "SataSalpSupport" = "1"
	register "SataMode" = "0"
	register "SataPortsEnable[0]" = "0"
	register "SataPortsEnable[1]" = "1"
	register "SataPortsEnable[2]" = "1"
	register "SataPortsDevSlp[0]" = "0"
	register "SataPortsDevSlp[1]" = "1"
	register "SataPortsDevSlp[2]" = "1"
	register "InternalGfx" = "1"
	register "SkipExtGfxScan" = "1"
	register "VmxEnable" = "1"

	register "speed_shift_enable" = "1"
	register "s0ix_enable" = "1"

	# Intel Common SoC Config
	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C
	register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)"	# Ext USB2 Port 3
	register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)"	# Ext USB2 Port 4
	register "usb2_ports[3]" = "USB2_PORT_EMPTY"
	register "usb2_ports[4]" = "USB2_PORT_EMPTY"
	register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)"	# Camera
	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# WWAN
	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# USH
	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# FPR in PB
	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 2230 (BT)

	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-C
	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"	# Ext USB3 Port 3
	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"	# Ext USB3 Port 4
	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 3042 (WWAN)
	register "usb3_ports[4]" = "USB3_PORT_EMPTY"
	register "usb3_ports[5]" = "USB3_PORT_EMPTY"

	# Intel Common SoC Config
	#+-------------------+---------------------------+
	#| Field             |  Value                    |
	#+-------------------+---------------------------+
	#| chipset_lockdown  | CHIPSET_LOCKDOWN_COREBOOT |
	#| I2C0              | Touchscreen               |
	#| I2C1              | Touchpad                  |
	#| I2C4              | H1 TPM                    |
	#+-------------------+---------------------------+
	register "common_soc_config" = "{
		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
		.i2c[0] = {
			.speed = I2C_SPEED_FAST,
		},
		.i2c[1] = {
			.speed = I2C_SPEED_FAST,
		},
		.i2c[4] = {
			.early_init = 1,
			.speed = I2C_SPEED_FAST,
		},
	}"

	# PCIe port 9 for LAN
	register "PcieRpEnable[8]" = "1"
	register "PcieClkSrcUsage[0]" = "8"
	register "PcieClkSrcClkReq[0]" = "0"

	# PCIe port 10 for M.2 2230 WLAN
	register "PcieRpEnable[9]" = "1"
	register "PcieClkSrcUsage[2]" = "9"
	register "PcieClkSrcClkReq[2]" = "2"

	# PCIe port 11 for card reader
	register "PcieRpEnable[10]" = "1"
	register "PcieClkSrcUsage[1]" = "10"
	register "PcieClkSrcClkReq[1]" = "1"

	# PCIe port 12 for M.2 3042
	register "PcieRpEnable[11]" = "1"
	register "PcieClkSrcUsage[3]" = "11"
	register "PcieClkSrcClkReq[3]" = "3"

	# PCIe port 13 for M.2 2280 SSD
	register "PcieRpEnable[12]" = "1"
	register "PcieClkSrcUsage[4]" = "12"
	register "PcieClkSrcClkReq[4]" = "4"

	device cpu_cluster 0 on
		device lapic 0 on end
	end
	device domain 0 on
		device pci 00.0 on  end # Host Bridge
		device pci 02.0 on  end # Integrated Graphics Device
		device pci 04.0 on  end # SA Thermal device
		device pci 12.0 on  end # Thermal Subsystem
		device pci 12.5 off end # UFS SCS
		device pci 12.6 off end # GSPI #2
		device pci 14.0 on  end # USB xHCI
		device pci 14.1 off end # USB xDCI (OTG)
		device pci 14.5 off end # SDCard
		device pci 15.0 on  end # I2C #0
		device pci 15.1 on
			chip drivers/i2c/hid
				register "generic.hid" = ""ACPI0C50""
				register "generic.desc" = ""Touchpad""
				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
				register "hid_desc_reg_offset" = "0x20"
				device i2c 2c on end
			end
		end # I2C #1
		device pci 15.2 off end # I2C #2
		device pci 15.3 off end # I2C #3
		device pci 16.0 on  end # Management Engine Interface 1
		device pci 16.1 off end # Management Engine Interface 2
		device pci 16.2 off end # Management Engine IDE-R
		device pci 16.3 off end # Management Engine KT Redirection
		device pci 16.4 off end # Management Engine Interface 3
		device pci 16.5 off end # Management Engine Interface 4
		device pci 17.0 on  end # SATA
		device pci 19.0 on
			chip drivers/i2c/tpm
				register "hid" = ""GOOG0005""
				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)"
				device i2c 50 on end
			end
		end # I2C #4
		device pci 19.1 off end # I2C #5
		device pci 19.2 on  end # UART #2
		device pci 1a.0 off end # eMMC
		device pci 1c.0 off end # PCI Express Port 1 (USB)
		device pci 1c.1 off end # PCI Express Port 2 (USB)
		device pci 1c.2 off end # PCI Express Port 3 (USB)
		device pci 1c.3 off end # PCI Express Port 4 (USB)
		device pci 1c.4 off end # PCI Express Port 5 (USB)
		device pci 1c.5 off end # PCI Express Port 6
		device pci 1c.6 off end # PCI Express Port 7
		device pci 1c.7 off end # PCI Express Port 8
		device pci 1d.0 on  end # PCI Express Port 9
		device pci 1d.1 on  end # PCI Express Port 10
		device pci 1d.2 on  end # PCI Express Port 11
		device pci 1d.3 on  end # PCI Express Port 12
		device pci 1d.4 on  end # PCI Express Port 13 (x4)
		device pci 1e.0 off end # UART #0
		device pci 1e.1 off end # UART #1
		device pci 1e.2 off end # GSPI #0
		device pci 1e.3 off end # GSPI #1
		device pci 1f.0 on  end # LPC/eSPI
		device pci 1f.1 on  end # P2SB
		device pci 1f.2 on  end # Power Management Controller
		device pci 1f.3 on  end # Intel HDA
		device pci 1f.4 on  end # SMBus
		device pci 1f.5 on  end # PCH SPI
		device pci 1f.6 on  end # GbE
	end
end