/* * This file is part of the coreboot project. * * Copyright (C) 2007-2010 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ // __PRE_RAM__ means: use "unsigned" for device, not a struct. #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0) static void ich7_enable_lpc(void) { // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); // Set COM1/COM2 decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); // Enable COM1/COM2/KBD/SuperIO1+2 pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | COMA_LPC_EN | COMB_LPC_EN); // Enable HWM at 0x290 pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0291); // io 0x300 decode pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301); } /* This box has one superio * Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. */ static void early_superio_config_w83627ehg(void) { pnp_devfn_t dev; dev = SUPERIO_DEV; pnp_enter_conf_state(dev); pnp_write_config(dev, 0x24, 0xc4); // PNPCVS pnp_write_config(dev, 0x29, 0x01); // GPIO settings pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02 pnp_write_config(dev, 0x2b, 0xc0); // GPIO settings? pnp_write_config(dev, 0x2c, 0x03); // GPIO settings? pnp_write_config(dev, 0x2d, 0x20); // GPIO settings? dev = PNP_DEV(0x4e, W83627EHG_SP1); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); pnp_set_irq(dev, PNP_IDX_IRQ0, 4); pnp_set_enable(dev, 1); dev = PNP_DEV(0x4e, W83627EHG_SP2); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); pnp_set_irq(dev, PNP_IDX_IRQ0, 3); // pnp_write_config(dev, 0xf1, 4); // IRMODE0 pnp_set_enable(dev, 1); dev = PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); //pnp_write_config(dev, 0xf0, 0x82); pnp_set_enable(dev, 1); dev = PNP_DEV(0x4e, W83627EHG_GPIO2); pnp_set_logical_device(dev); pnp_set_enable(dev, 1); // Just enable it dev = PNP_DEV(0x4e, W83627EHG_GPIO3); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient dev = PNP_DEV(0x4e, W83627EHG_FDC); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); dev = PNP_DEV(0x4e, W83627EHG_PP); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); /* Enable HWM */ dev = PNP_DEV(0x4e, W83627EHG_HWM); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); pnp_set_enable(dev, 1); pnp_exit_conf_state(dev); } static void rcba_config(void) { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; //RCBA32(0x001c) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00042210; /* Device 1d interrupt pin register */ RCBA32(D28IP) = 0x00214321; /* dev irq route register */ RCBA16(D31IR) = 0x0132; RCBA16(D30IR) = 0x0146; RCBA16(D29IR) = 0x0237; RCBA16(D28IR) = 0x3201; RCBA16(D27IR) = 0x0146; /* Enable IOAPIC */ RCBA8(OIC) = 0x03; /* Enable PCIe Root Port Clock Gate */ // RCBA32(0x341c) = 0x00000001; } static void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; // program secondary mlt XXX byte? pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); // reset rtc power status reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); reg8 &= ~(1 << 2); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); // usb transient disconnect reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); reg8 |= (3 << 0); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); reg32 |= (1 << 31) | (1 << 27); pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); RCBA32(0x0088) = 0x0011d000; RCBA16(0x01fc) = 0x060f; RCBA32(0x01f4) = 0x86000040; RCBA32(0x0214) = 0x10030549; RCBA32(0x0218) = 0x00020504; RCBA8(0x0220) = 0xc5; reg32 = RCBA32(GCS); reg32 |= (1 << 6); RCBA32(GCS) = reg32; reg32 = RCBA32(0x3430); reg32 &= ~(3 << 0); reg32 |= (1 << 0); RCBA32(0x3430) = reg32; RCBA16(0x0200) = 0x2008; RCBA8(0x2027) = 0x0d; RCBA16(0x3e08) |= (1 << 7); RCBA16(0x3e48) |= (1 << 7); RCBA32(0x3e0e) |= (1 << 7); RCBA32(0x3e4e) |= (1 << 7); // next step only on ich7m b0 and later: reg32 = RCBA32(0x2034); reg32 &= ~(0x0f << 16); reg32 |= (5 << 16); RCBA32(0x2034) = reg32; } void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; if (bist == 0) enable_lapic(); ich7_enable_lpc(); early_superio_config_w83627ehg(); /* Set up the console */ console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); outb(0x6, 0xcf9); halt(); } /* Perform some early chipset initialization required * before RAM initialization can work */ i945_early_initialization(); s3resume = southbridge_detect_s3_resume(); /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif sdram_initialize(s3resume ? 2 : 0, NULL); /* Perform some initialization that must run before stage2 */ early_ich7_init(); /* This should probably go away. Until now it is required * and mainboard specific */ rcba_config(); /* Chipset Errata! */ fixup_i945_errata(); /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(s3resume); }