chip northbridge/intel/sandybridge
	# IGD Displays
	register "gfx" = "GMA_STATIC_DISPLAYS(0)"

	# Enable DisplayPort 1 Hotplug with 6ms pulse
	register "gpu_dp_d_hotplug" = "0x06"

	# Enable DisplayPort 0 Hotplug with 6ms pulse
	register "gpu_dp_c_hotplug" = "0x06"

	# Enable DVI Hotplug with 6ms pulse
	register "gpu_dp_b_hotplug" = "0x06"

	device cpu_cluster 0 on
		chip cpu/intel/model_206ax
			# Magic APIC ID to locate this chip
			device lapic 0x0 on end
			device lapic 0xacac off end

			register "c1_battery" = "3"	# ACPI(C1) = MWAIT(C3)
			register "c2_battery" = "4"	# ACPI(C2) = MWAIT(C6)
			register "c3_battery" = "5"	# ACPI(C3) = MWAIT(C7)

			register "c1_acpower" = "3"	# ACPI(C1) = MWAIT(C3)
			register "c2_acpower" = "4"	# ACPI(C2) = MWAIT(C6)
			register "c3_acpower" = "5"	# ACPI(C3) = MWAIT(C7)
		end
	end

	device domain 0 on
		device pci 00.0 on  end	# host bridge
		device pci 02.0 on  end	# vga controller

		chip southbridge/intel/bd82x6x	# Intel Series 6 Cougar Point PCH
			# GPI routing
			#  0 No effect (default)
			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
			#  2 SCI (if corresponding GPIO_EN bit is also set)
			register "gpi1_routing"  = "1"
			register "gpi14_routing" = "2"
			register "alt_gp_smi_en" = "0x0002"
			register "gpe0_en" = "0x4000"

			register "sata_port_map" = "0x3f"

			register "gen1_dec" = "0x00fc1601"
			# runtime_port registers
			register "gen2_dec" = "0x000c0181"
			# SuperIO range is 0x700-0x73f
			register "gen3_dec" = "0x003c0701"

			register "c2_latency" = "1"

			device pci 16.0 on  end	# Management Engine Interface 1
			device pci 16.1 off end	# Management Engine Interface 2
			device pci 16.2 off end	# Management Engine IDE-R
			device pci 16.3 off end	# Management Engine KT
			device pci 19.0 off end	# Intel Gigabit Ethernet
			device pci 1a.0 on  end	# USB2 EHCI #2
			device pci 1b.0 on  end	# High Definition Audio
			device pci 1c.0 on  end	# PCIe Port #1 (WLAN)
			device pci 1c.1 off end	# PCIe Port #2
			device pci 1c.2 on  end	# PCIe Port #3 (Debug)
			device pci 1c.3 on  end	# PCIe Port #4 (LAN)
			device pci 1c.4 off end	# PCIe Port #5
			device pci 1c.5 off end	# PCIe Port #6
			device pci 1c.6 off end	# PCIe Port #7
			device pci 1c.7 off end	# PCIe Port #8
			device pci 1d.0 on  end	# USB2 EHCI #1
			device pci 1e.0 off end	# PCI bridge
			device pci 1f.0 on  end	# LPC bridge
			device pci 1f.2 on  end	# SATA Controller 1
			device pci 1f.3 on  end	# SMBus
			device pci 1f.5 off end	# SATA Controller 2
			device pci 1f.6 on  end	# Thermal
		end
	end
end