##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2009 coresystems GmbH
## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##

chip northbridge/intel/i945
	device domain 0 on
		device pci 00.0 on # Host bridge
			subsystemid 0x17aa 0x2017
		end
		device pci 01.0 on # PEG
			device pci 00.0 on end # VGA
		end
		chip southbridge/intel/i82801gx
			device pci 1c.0 on # PCI Express Port 1
				subsystemid 0x17aa 0x2011
			end
			device pci 1c.1 on # PCI Express Port 2
				subsystemid 0x17aa 0x2011
			end
			device pci 1c.2 on # PCI Express Port 3
				subsystemid 0x17aa 0x2011
			end
			device pci 1c.3 on # PCI Express Port 4
				subsystemid 0x17aa 0x2011
			end
			device pci 1e.0 on # PCI Bridge
				chip southbridge/ti/pci1x2x
					device pci 00.0 on
						subsystemid 0x17aa 0x2013
					end
				end
			end
			device pci 1f.0 on # PCI-LPC bridge
				chip superio/nsc/pc87384
					device pnp 2e.2 off # Serial Port / IR
						irq 0x70 = 3
					end
				end
			end
			device pci 1f.3 on # SMBUS
				chip drivers/i2c/ck505
					register "mask" = "{ 0xff, 0xff, 0xff,
						0xff, 0xff, 0xff, 0xff, 0xff }"
					# vendor clockgen setup
					register "regs" = "{ 0x6d, 0xff, 0xff,
						0x20, 0x41, 0x7f, 0x18, 0x00 }"
				end
			end
		end
	end
end