#
# This file is part of the coreboot project.
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
chip northbridge/amd/agesa/family14/root_complex
	device cpu_cluster 0 on
		chip cpu/amd/agesa/family14
			device lapic 0 on end
		end
	end
	device domain 0 on
		subsystemid 0x1022 0x1510 inherit
		chip northbridge/amd/agesa/family14
			device pci 0.0 on end # Root Complex
			device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
			device pci 4.0 on end # PCIE P2P bridge on-board NIC
			device pci 5.0 off end # PCIE P2P bridge
			device pci 6.0 off end # PCIE P2P bridge
			device pci 7.0 off end # PCIE P2P bridge
			device pci 8.0 off end # NB/SB Link P2P bridge
		end # agesa northbridge

		chip southbridge/amd/cimx/sb800
			device pci 11.0 on end # SATA
			device pci 12.0 on end # OHCI USB 0-4
			device pci 12.2 on end # EHCI USB 0-4
			device pci 13.0 on end # OHCI USB 5-9
			device pci 13.2 on end # EHCI USB 5-9
			device pci 14.0 on end # SM
			device pci 14.1 off end # IDE	0x439c
			device pci 14.2 on end # HDA	0x4383
			device pci 14.3 on # LPC		0x439d
				chip superio/smsc/smscsuperio
					device pnp 4e.0 off end		# Floppy
					device pnp 4e.3 off end		# Parallel Port
					device pnp 4e.4 on		# COM1
						io 0x60 = 0x3f8
						irq 0x70 = 4
					end
					device pnp 4e.5 on		# COM2
						io 0x60 = 0x2f8
						irq 0x70 = 3
					end
					device pnp 4e.7 on		# Keyboard
						io 0x60 = 0x60
						io 0x62 = 0x64
						irq 0x70 = 1
						irq 0x72 = 12
					end
					device pnp 4e.A on		# Runtime Regs
						io 0x60 = 0x0E00
						drq 0xF0 = 0x0B # no 32kHz
					end
				end # smscsuperio
			end #LPC

			device pci 14.4 on  end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
			device pci 14.5 off end # OHCI FS/LS USB
			device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
			device pci 15.0 off end # PCIe PortA
			device pci 15.1 off end # PCIe PortB
			device pci 15.2 off end # PCIe PortC
			device pci 15.3 off end # PCIe PortD
			device pci 16.0 on  end # OHCI USB 10-13
			device pci 16.2 on  end # EHCI USB 10-13

			register "gpp_configuration" = "4" #1:1:1:1
			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
		end	#southbridge/amd/cimx/sb800

		chip northbridge/amd/agesa/family14

			# These seem unnecessary
			device pci 18.0 on end
			device pci 18.1 on end
			device pci 18.2 on end
			device pci 18.3 on end
			device pci 18.4 on end
			device pci 18.5 on end
			device pci 18.6 on end
			device pci 18.7 on end

			register "spdAddrLookup" = "
			{
				{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
			}"

		end # agesa northbridge

	end #domain
end #northbridge/amd/agesa/family14/root_complex