# SPDX-License-Identifier: GPL-2.0-only

chip soc/intel/cannonlake
	# FSP configuration
	register "SaGv" = "SaGv_Enabled"
	register "RMT" = "0"

	register "PchHdaDspEnable" = "0"
        register "PchHdaAudioLinkHda" = "1"

	device cpu_cluster 0 on
		device lapic 0 on end
	end

	device domain 0 on
		device pci 00.0 on	end	# Host Bridge
		device pci 01.0 off	end	# PCIe x16
		device pci 01.1 off	end	# PCIe x8
		device pci 01.2 off	end	# PCIe x4
		device pci 02.0 on	end	# Integrated Graphics Device
		device pci 04.0 on	end	# SA Thermal device
		device pci 05.0 off	end	# Imaging Processing Unit
		device pci 08.0 off	end	# Gaussian mixture model, Neural network accelerator
		device pci 12.0 on	end	# Thermal Subsystem
		device pci 12.5 off	end	# UFS SCS
		device pci 12.6 off	end	# GSPI #2
		device pci 13.0 off	end	# ISH
		device pci 14.0 on		# USB xHCI
			# USB2
			register "usb2_ports[0]"  = "USB2_PORT_TYPE_C(OC2)"     # Type-C?
			register "usb2_ports[1]"  = "USB2_PORT_MID(OC0)"        # single blue
			register "usb2_ports[4]"  = "USB2_PORT_MID(OC_SKIP)"    # SIMATIC NET CP 5711
			register "usb2_ports[7]"  = "USB2_PORT_MID(OC1)"        # upper blue
			register "usb2_ports[8]"  = "USB2_PORT_MID(OC4)"        # lower blue
			register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)"    # STM SC?
			# USB3
			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"     # Type-C?
			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"     # upper blue
			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC4)"     # lower blue
			register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Realtek storage?
			register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"     # single blue
		end
		device pci 14.1 off	end	# USB xDCI (OTG)
		device pci 14.2 on	end	# Shared SRAM
		device pci 14.3 off	end	# CNVi Wifi
		device pci 14.5 off	end	# SDCard
		device pci 15.0 off	end	# I2C #0
		device pci 15.1 off	end	# I2C #1
		device pci 15.2 off	end	# I2C #2
		device pci 15.3 off	end	# I2C #3
		device pci 16.0 on	end	# Management Engine Interface 1
		device pci 16.1 off	end	# Management Engine Interface 2
		device pci 16.2 off	end	# Management Engine IDE-R
		device pci 16.3 off	end	# Management Engine KT Redirection
		device pci 16.4 off	end	# Management Engine Interface 3
		device pci 16.5 off	end	# Management Engine Interface 4
		device pci 17.0 on		# SATA
			register "SataSalpSupport" = "1"
			register "SataPortsEnable[0]" = "1"	# HDD / SSD
			register "SataPortsEnable[1]" = "1"	# ODD
			register "SataPortsEnable[3]" = "1"	# HDD / SSD

			register "SataPortsDevSlp[0]" = "1"	# M.2
			register "SataPortsDevSlp[2]" = "1"	# HDD / SSD
		end
		device pci 19.0 off	end	# I2C #4
		device pci 19.1 off	end	# I2C #5
		device pci 19.2 off	end	# UART #2
		device pci 1a.0 off	end	# eMMC
		device pci 1c.0 off	end	# PCI Express Port 1
		device pci 1c.1 off	end	# PCI Express Port 2
		device pci 1c.2 off	end	# PCI Express Port 3
		device pci 1c.3 off	end	# PCI Express Port 4
		device pci 1c.4 on		# PCI Express Port 5
			device pci 00.0 on end	# x1 i219
			register "PcieRpEnable[4]" = "1"
			register "PcieClkSrcUsage[4]" = "0x70"
			register "PcieClkSrcClkReq[4]" = "4"
			register "PcieRpSlotImplemented[4]" = "0"
		end
		device pci 1c.5 on		# PCI Express Port 6
			device pci 00.0 on end	# x1 i210
			register "PcieRpEnable[5]" = "1"
			register "PcieClkSrcUsage[5]" = "5"
			register "PcieClkSrcClkReq[5]" = "5"
			register "PcieRpSlotImplemented[5]" = "0"
		end
		device pci 1c.6 on		# PCI Express Port 7
			device pci 00.0 on end	# x1 M.2 (WLAN / BT)
			register "PcieRpEnable[6]" = "1"
			register "PcieRpSlotImplemented[6]" = "1"
		end
		device pci 1c.7 off	end	# PCI Express Port 8
		device pci 1d.0 off	end	# PCI Express Port 9
		device pci 1d.1 off	end	# PCI Express Port 10
		device pci 1d.2 off	end	# PCI Express Port 11
		device pci 1d.3 off	end	# PCI Express Port 12
		device pci 1d.4 off	end	# PCI Express Port 13
		device pci 1d.5 off	end	# PCI Express Port 14
		device pci 1d.6 off	end	# PCI Express Port 15
		device pci 1d.7 off	end	# PCI Express Port 16
		device pci 1b.0 on		# PCI Express Port 17
			device pci 00.0 on end	# x4 M.2/M
			register "PcieRpEnable[16]" = "1"
			register "PcieClkSrcUsage[7]" = "16"
			register "PcieClkSrcClkReq[7]" = "7"
			register "PcieRpSlotImplemented[16]" = "1"
		end
		device pci 1b.1 off	end	# PCI Express Port 18
		device pci 1b.2 off	end	# PCI Express Port 19
		device pci 1b.3 off	end	# PCI Express Port 20
		device pci 1b.4 off	end	# PCI Express Port 21
		device pci 1b.5 off	end	# PCI Express Port 22
		device pci 1b.6 off	end	# PCI Express Port 23
		device pci 1b.7 off	end	# PCI Express Port 24
		device pci 1e.0 off	end	# UART #0
		device pci 1e.1 off	end	# UART #1
		device pci 1e.2 off	end	# GSPI #0
		device pci 1e.3 off	end	# GSPI #1
		device pci 1f.0 on		# LPC Interface
			chip drivers/pc80/tpm
				device pnp 0c31.0 on end
			end
		end
		device pci 1f.1 on	end	# P2SB
		device pci 1f.2 on	end	# Power Management Controller
		device pci 1f.3 on	end	# Intel HDA
		device pci 1f.4 on	end	# SMBus
		device pci 1f.5 on	end	# PCH SPI
		device pci 1f.6 on	end	# GbE
		device pci 1f.7 off	end	# TraceHub
	end
end