#
# This file is part of the coreboot project.
#
# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
chip northbridge/amd/agesa/family15/root_complex
	device cpu_cluster 0 on
		chip cpu/amd/agesa/family15
			device lapic 0x10 on end
		end
	end
	device domain 0 on
		subsystemid 0x15d9 0xab11 inherit #Supermicro
		chip northbridge/amd/agesa/family15 # CPU side of HT root complex
			device pci 18.0 on     # Put IO-HUB at link_num 0, Instead of HT Link topology
				chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex
					device pci 0.0 on  end # HT Root Complex 0x9600
					device pci 0.1 on end # CLKCONFIG
					device pci 2.0 on  end # GPP1 Port0  x16 SLOT4, 0x5A16
					device pci 3.0 on end # GPP1 Port1
					device pci 4.0 on end # GPP3a Port0  x4 SAS
					device pci 5.0 off end # GPP3a Port1
					device pci 6.0 off end # GPP3a Port2
					device pci 7.0 off end # GPP3a Port3
					device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time
					device pci 9.0 on end # GPP3a Port4  x1 NC
					device pci a.0 on end # GPP3a Port5  x1 NC
					device pci b.0 off end # GPP2 Port0 (Not for sr5650)
					device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670)
					device pci d.0 off  end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576
					register "gpp1_configuration" = "1"   # Configuration 16:0 default
					#register "gpp2_configuration" = "0"   # Configuration 8:8
					register "gpp3a_configuration" = "2"   # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1
					register "port_enable" = "0x61f"
				end #northbridge/amd/cimx/rd890
				chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pci bus
					device pci 11.0 on end # SATA
					device pci 12.0 on end # USB1
					device pci 12.1 on end # USB1
					device pci 12.2 on end # USB1
					device pci 13.0 on end # USB2
					device pci 13.1 on end # USB2
					device pci 13.2 on end # USB2
					device pci 14.0 on end # SM
					device pci 14.1 off end # IDE  0x439c
					device pci 14.2 off end # HDA  0x4383, h8scm not have codec.
					device pci 14.3 on # LPC  0x439d
						chip superio/winbond/w83627dhg
							device pnp 2e.0 off #  Floppy
								io 0x60 = 0x3f0
								irq 0x70 = 6
								drq 0x74 = 2
							end
							device pnp 2e.1 off #  Parallel Port
								io 0x60 = 0x378
								irq 0x70 = 7
							end
							device pnp 2e.2 on  #  Com1
								io 0x60 = 0x3f8
								irq 0x70 = 4
							end
							device pnp 2e.3 on  #  Com2
								io 0x60 = 0x2f8
								irq 0x70 = 3
							end
							## though UARTs are on the NUVOTON BMC, superio only used to support PS2 KB/MS##
							device pnp 2e.5 on #  PS/2 keyboard & mouse
								io 0x60 = 0x60
								io 0x62 = 0x64
								irq 0x70 = 0x01 #keyboard
								irq 0x72 = 0x0C #mouse
							end
							device pnp 2e.6 off #  SPI
							end
							device pnp 2e.307 off #  GPIO6
							end
							device pnp 2e.8 off #  WDTO#, PLED
							end
							device pnp 2e.009 off #  GPIO2
							end
							device pnp 2e.109 off #  GPIO3
							end
							device pnp 2e.209 off #  GPIO4
							end
							device pnp 2e.309 off #  GPIO5
							end
							device pnp 2e.a off #  ACPI
							end
							device pnp 2e.b off # HWM
								io 0x60 = 0x290
							end
							device pnp 2e.c off # PECI, SST
							end
						end #superio/winbond/w83627dhg
						chip drivers/i2c/w83795
							register "fanin_ctl1" = "0xff"			# Enable monitoring of FANIN1 - FANIN8
							register "fanin_ctl2" = "0x00"			# Connect FANIN11 - FANIN14 to alternate functions
							register "temp_ctl1" = "0x2a"			# Enable monitoring of DTS, VSEN12, and VSEN13
							register "temp_ctl2" = "0x01"			# Enable monitoring of TD1/TR1
							register "temp_dtse" = "0x03"			# Enable DTS1 and DTS2
							register "volt_ctl1" = "0xff"			# Enable monitoring of VSEN1 - VSEN8
							register "volt_ctl2" = "0xf7"			# Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT
							register "temp1_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp1)
							register "temp2_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp2)
							register "temp3_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp3)
							register "temp4_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp4)
							register "temp5_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp5)
							register "temp6_fan_select" = "0x00"		# All fans to manual mode (no dependence on Temp6)
							register "temp1_source_select" = "0x00"		# Use TD1/TR1 as data source for Temp1
							register "temp2_source_select" = "0x00"		# Use TD2/TR2 as data source for Temp2
							register "temp3_source_select" = "0x00"		# Use TD3/TR3 as data source for Temp3
							register "temp4_source_select" = "0x00"		# Use TD4/TR4 as data source for Temp4
							register "temp5_source_select" = "0x00"		# Use TR5 as data source for Temp5
							register "temp6_source_select" = "0x00"		# Use TR6 as data source for Temp6
							register "tr1_critical_temperature" = "85"	# Set TD1/TR1 critical temperature to 85°C
							register "tr1_critical_hysteresis" = "80"	# Set TD1/TR1 critical hysteresis temperature to 80°C
							register "tr1_warning_temperature" = "70"	# Set TD1/TR1 warning temperature to 70°C
							register "tr1_warning_hysteresis" = "65"	# Set TD1/TR1 warning hysteresis temperature to 65°C
							register "dts_critical_temperature" = "85"	# Set DTS (CPU) critical temperature to 85°C
							register "dts_critical_hysteresis" = "80"	# Set DTS (CPU) critical hysteresis temperature to 80°C
							register "dts_warning_temperature" = "70"	# Set DTS (CPU) warning temperature to 70°C
							register "dts_warning_hysteresis" = "65"	# Set DTS (CPU) warning hysteresis temperature to 65°C
							register "temp1_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
							register "temp2_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
							register "temp3_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
							register "temp4_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
							register "temp5_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
							register "temp6_critical_temperature" = "80"	# Set Temp1 critical temperature to 80°C
							register "temp1_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
							register "temp2_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
							register "temp3_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
							register "temp4_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
							register "temp5_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
							register "temp6_target_temperature" = "80"	# Set Temp1 target temperature to 80°C
							register "fan1_nonstop" = "7"			# Set Fan 1 minimum speed
							register "fan2_nonstop" = "7"			# Set Fan 2 minimum speed
							register "fan3_nonstop" = "7"			# Set Fan 3 minimum speed
							register "fan4_nonstop" = "7"			# Set Fan 4 minimum speed
							register "fan5_nonstop" = "7"			# Set Fan 5 minimum speed
							register "fan6_nonstop" = "7"			# Set Fan 6 minimum speed
							register "fan7_nonstop" = "7"			# Set Fan 7 minimum speed
							register "fan8_nonstop" = "7"			# Set Fan 8 minimum speed
							register "default_speed" = "100"		# All fans to full speed on power up
							register "fan1_duty" = "100"			# Fan 1 to full speed
							register "fan2_duty" = "100"			# Fan 2 to full speed
							register "fan3_duty" = "100"			# Fan 3 to full speed
							register "fan4_duty" = "100"			# Fan 4 to full speed
							register "fan5_duty" = "100"			# Fan 5 to full speed
							register "fan6_duty" = "100"			# Fan 6 to full speed
							register "fan7_duty" = "100"			# Fan 7 to full speed
							register "fan8_duty" = "100"			# Fan 8 to full speed
							register "vcore1_high_limit_mv" = "1500"	# VCORE1 (Node 0) high limit to 1.5V
							register "vcore1_low_limit_mv" = "900"		# VCORE1 (Node 0) low limit to 0.9V
							register "vcore2_high_limit_mv" = "1500"	# VCORE2 (Node 1) high limit to 1.5V
							register "vcore2_low_limit_mv" = "900"		# VCORE2 (Node 1) low limit to 0.9V
							register "vsen3_high_limit_mv" = "1600"		# VSEN1 (Node 0 RAM voltage) high limit to 1.6V
							register "vsen3_low_limit_mv" = "1100"		# VSEN1 (Node 0 RAM voltage) low limit to 1.1V
							register "vsen4_high_limit_mv" = "1600"		# VSEN2 (Node 1 RAM voltage) high limit to 1.6V
							register "vsen4_low_limit_mv" = "1100"		# VSEN2 (Node 1 RAM voltage) low limit to 1.1V
							register "vsen5_high_limit_mv" = "1250"		# VSEN5 (Node 0 HT link voltage) high limit to 1.25V
							register "vsen5_low_limit_mv" = "1150"		# VSEN5 (Node 0 HT link voltage) low limit to 1.15V
							register "vsen6_high_limit_mv" = "1250"		# VSEN6 (Node 1 HT link voltage) high limit to 1.25V
							register "vsen6_low_limit_mv" = "1150"		# VSEN6 (Node 1 HT link voltage) low limit to 1.15V
							register "vsen7_high_limit_mv" = "1150"		# VSEN7 (Northbridge core voltage) high limit to 1.15V
							register "vsen7_low_limit_mv" = "1050"		# VSEN7 (Northbridge core voltage) low limit to 1.05V
							register "vsen8_high_limit_mv" = "1900"		# VSEN8 (+1.8V) high limit to 1.9V
							register "vsen8_low_limit_mv" = "1700"		# VSEN8 (+1.8V) low limit to 1.7V
							register "vsen9_high_limit_mv" = "1250"		# VSEN9 (+1.2V) high limit to 1.25V
							register "vsen9_low_limit_mv" = "1150"		# VSEN9 (+1.2V) low limit to 1.15V
							register "vsen10_high_limit_mv" = "1150"	# VSEN10 (+1.1V) high limit to 1.15V
							register "vsen10_low_limit_mv" = "1050"		# VSEN10 (+1.1V) low limit to 1.05V
							register "vsen11_high_limit_mv" = "1625"	# VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V
							register "vsen11_low_limit_mv" = "1500"		# VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V
							register "vsen12_high_limit_mv" = "1083"	# VSEN12 (+12V, scaling factor ~12) high limit to 13V
							register "vsen12_low_limit_mv" = "917"		# VSEN12 (+12V, scaling factor ~12) low limit to 11V
							register "vsen13_high_limit_mv" = "1625"	# VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V
							register "vsen13_low_limit_mv" = "1500"		# VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V
							register "vdd_high_limit_mv" = "3500"		# 3VDD high limit to 3.5V
							register "vdd_low_limit_mv" = "3100"		# 3VDD low limit to 3.1V
							register "vsb_high_limit_mv" = "3500"		# 3VSB high limit to 3.5V
							register "vsb_low_limit_mv" = "3100"		# 3VSB low limit to 3.1V
							register "vbat_high_limit_mv" = "3500"		# VBAT (+3V) high limit to 3.5V
							register "vbat_low_limit_mv" = "2500"		# VBAT (+3V) low limit to 2.5V
							register "smbus_aux" = "0"			# Device located on primary SMBUS
							device pnp 5e on #hwm
							end
						end #drivers/i2c/w83795
					end # LPC
					device pci 14.4 on end # PCI 0x4384
					device pci 14.5 on end # USB 3
					register "boot_switch_sata_ide" = "0"   # 0: boot from SATA. 1: IDE
				end # southbridge/amd/cimx/sb700
			end # device pci 18.0

			device pci 18.1 on end
			device pci 18.2 on end
			device pci 18.3 on end
			device pci 18.4 on end
			device pci 18.5 on end #f15

			register "spdAddrLookup" = "
			{
				{ {0xA4, 0xA6}, {0xA0, 0xA2}, {0x00, 0x00}, {0x00, 0x00}, }, // socket 0
				{ {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 (unused)
			}"
		end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
	end #domain
end #northbridge/amd/agesa/family15/root_complex