uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses LB_CKS_RANGE_START uses LB_CKS_RANGE_END uses LB_CKS_LOC uses MAINBOARD uses ARCH uses HARD_RESET_BUS uses HARD_RESET_DEVICE uses HARD_RESET_FUNCTION # # ### ### Set all of the defaults for an x86 architecture ### # # ### ### Build the objects we have code for in this directory. ### ##object mainboard.o config chip.h register "fixup_scsi" = "1" register "fixup_vga" = "1" ## ## Move the default LinuxBIOS cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 default LB_CKS_LOC=123 driver mainboard.o #dir /drivers/adaptec/7902 #dir /drivers/si/3114 #dir /drivers/intel/82551 #dir /drivers/broadcom/tg3_ipmi dir /drivers/ati/ragexl #object reset.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end # default HARD_RESET_BUS=1 default HARD_RESET_DEVICE=4 default HARD_RESET_FUNCTION=0 # arch i386 end #cpu k8 end # ### ### Build our 16 bit and 32 bit linuxBIOS entry code ### mainboardinit cpu/i386/entry16.inc mainboardinit cpu/i386/entry32.inc mainboardinit cpu/i386/bist32.inc ldscript /cpu/i386/entry16.lds ldscript /cpu/i386/entry32.lds # ### ### Build our reset vector (This is where linuxBIOS is entered) ### if USE_FALLBACK_IMAGE mainboardinit cpu/i386/reset16.inc ldscript /cpu/i386/reset16.lds else mainboardinit cpu/i386/reset32.inc ldscript /cpu/i386/reset32.lds end # #### Should this be in the northbridge code? mainboardinit arch/i386/lib/cpu_reset.inc # ### ### Include an id string (For safe flashing) ### mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds # #### #### This is the early phase of linuxBIOS startup #### Things are delicate and we test to see if we should #### failover to another image. #### #option MAX_REBOOT_CNT=2 if USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end # ### ### Setup our mtrrs ### mainboardinit cpu/k8/earlymtrr.inc ### ### Only the bootstrap cpu makes it here. ### Failover if we need to ### # if USE_FALLBACK_IMAGE mainboardinit ./failover.inc end # # ### ### Setup the serial port ### mainboardinit pc80/serial.inc mainboardinit arch/i386/lib/console.inc mainboardinit cpu/i386/bist32_fail.inc # #### #### O.k. We aren't just an intermediary anymore! #### # ### ### Romcc output ### makerule ./failover.E depends "$(MAINBOARD)/failover.c" action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E" end makerule ./failover.inc depends "./romcc ./failover.E" action "./romcc -O2 -o failover.inc --label-prefix=failover ./failover.E"end makerule ./auto.E depends "$(MAINBOARD)/auto.c option_table.h" action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" end makerule ./auto.inc depends "./romcc ./auto.E" action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E" end mainboardinit cpu/k8/enable_mmx_sse.inc mainboardinit ./auto.inc mainboardinit cpu/k8/disable_mmx_sse.inc # ### ### Include the secondary Configuration files ### dir /pc80 northbridge amd/amdk8 "mc0" pci 0:18.0 pci 0:18.0 pci 0:18.0 pci 0:18.1 pci 0:18.2 pci 0:18.3 southbridge amd/amd8131 "amd8131" link 2 pci 0:0.0 pci 0:0.1 pci 0:1.0 pci 0:1.1 end southbridge amd/amd8111 "amd8111" link 2 pci 0:0.0 pci 0:1.0 on pci 0:1.1 on pci 0:1.2 on pci 0:1.3 on pci 0:1.5 off pci 0:1.6 off pci 1:0.0 on pci 1:0.1 on pci 1:0.2 off pci 1:1.0 off superio winbond/w83627hf link 1 pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 pnp 2e.1 off # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 pnp 2e.3 off # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 pnp 2e.5 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 pnp 2e.6 off # CIR pnp 2e.7 off # GAME_MIDI_GIPO1 pnp 2e.8 off # GPIO2 pnp 2e.9 off # GPIO3 pnp 2e.a off # ACPI pnp 2e.b on # HW Monitor io 0x60 = 0x290 end end end northbridge amd/amdk8 "mc1" pci 0:19.0 pci 0:19.0 pci 0:19.0 pci 0:19.1 pci 0:19.2 pci 0:19.3 end #dir /bioscall cpu k8 "cpu0" register "ldt0" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}" end cpu k8 "cpu1" end