config SOC_INTEL_CANNONLAKE bool help Intel Cannonlake support if SOC_INTEL_CANNONLAKE config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_NHLT select ARCH_BOOTBLOCK_X86_32 select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select GENERIC_GPIO_LIB select HAVE_FSP_GOP select HAVE_HARD_RESET select HAVE_INTEL_FIRMWARE select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP select IOAPIC select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 select POSTCAR_CONSOLE select POSTCAR_STAGE select REG_SCRIPT select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE select SMM_TSEG select SMP select SOC_AHCI_PORT_IMPLEMENTED_INVERT select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_DSP select SOC_INTEL_COMMON_BLOCK_EBDA select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GRAPHICS select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_ITSS select SOC_INTEL_COMMON_BLOCK_I2C select SOC_INTEL_COMMON_BLOCK_LPC select SOC_INTEL_COMMON_BLOCK_LPSS select SOC_INTEL_COMMON_BLOCK_P2SB select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_PMC select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SATA select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_XDCI select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO config UART_DEBUG bool "Enable UART debug port." default y select CONSOLE_SERIAL select BOOTBLOCK_CONSOLE select DRIVERS_UART select DRIVERS_UART_8250MEM_32 select NO_UART_ON_SUPERIO config UART_FOR_CONSOLE int "Index for LPSS UART port to use for console" default 2 if DRIVERS_UART_8250MEM_32 default 0 help Index for LPSS UART port to use for console: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 config DCACHE_RAM_BASE default 0xfef00000 config DCACHE_RAM_SIZE default 0x40000 help The size of the cache-as-ram region required during bootblock and/or romstage. config DCACHE_BSP_STACK_SIZE hex default 0x4000 help The amount of anticipated stack usage in CAR by bootblock and other stages. config IFD_CHIPSET string default "cnl" config IED_REGION_SIZE hex default 0x400000 config HEAP_SIZE hex default 0x8000 config NHLT_DMIC_1CH_16B bool depends on ACPI_NHLT default n help Include DSP firmware settings for 1 channel 16B DMIC array. config NHLT_DMIC_2CH_16B bool depends on ACPI_NHLT default n help Include DSP firmware settings for 2 channel 16B DMIC array. config NHLT_DMIC_4CH_16B bool depends on ACPI_NHLT default n help Include DSP firmware settings for 4 channel 16B DMIC array. config NHLT_MAX98357 bool depends on ACPI_NHLT default n help Include DSP firmware settings for headset codec. config NHLT_MAX98373 bool depends on ACPI_NHLT default n help Include DSP firmware settings for headset codec. config NHLT_DA7219 bool depends on ACPI_NHLT default n help Include DSP firmware settings for headset codec. config MAX_ROOT_PORTS int default 16 config SMM_TSEG_SIZE hex default 0x800000 config SMM_RESERVED_SIZE hex default 0x200000 config PCR_BASE_ADDRESS hex default 0xfd000000 help This option allows you to select MMIO Base Address of sideband bus. config CPU_BCLK_MHZ int default 100 config SOC_INTEL_CANNONLAKE_LPDDR4_INIT bool default n config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 120 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int default 3 # Clock divider parameters for 115200 baud rate config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex default 0x30 config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL hex default 0xc35 config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_OPROM_MATTERS select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH config C_ENV_BOOTBLOCK_SIZE hex default 0x8000 choice prompt "Cache-as-ram implementation" default USE_CANNONLAKE_CAR_NEM_ENHANCED if MAINBOARD_HAS_CHROMEOS default USE_CANNONLAKE_FSP_CAR help This option allows you to select how cache-as-ram (CAR) is set up. config USE_CANNONLAKE_CAR_NEM_ENHANCED bool "Enhanced Non-evict mode" select SOC_INTEL_COMMON_BLOCK_CAR select INTEL_CAR_NEM_ENHANCED help A current limitation of NEM (Non-Evict mode) is that code and data sizes are derived from the requirement to not write out any modified cache line. With NEM, if there is no physical memory behind the cached area, the modified data will be lost and NEM results will be inconsistent. ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. config USE_CANNONLAKE_FSP_CAR bool "Use FSP CAR" select FSP_CAR help Use FSP APIs to initialize and tear down the Cache-As-Ram. endchoice endif