config SOC_INTEL_COMMON_BLOCK_PMC
	depends on SOC_INTEL_COMMON_BLOCK_GPIO
	depends on ACPI_INTEL_HARDWARE_SLEEP_VALUES
	bool
	select HAVE_POWER_STATE_AFTER_FAILURE
	select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
	help
	  Intel Processor common code for Power Management controller(PMC)
	  subsystem

if SOC_INTEL_COMMON_BLOCK_PMC

config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
	default y

endif # SOC_INTEL_COMMON_BLOCK_PMC

config PMC_INVALID_READ_AFTER_WRITE
	bool
	default n
	help
	  Enable this for PMC devices where a read back of ACPI BAR and
	  IO access bit does not return the previously written value.

config PMC_GLOBAL_RESET_ENABLE_LOCK
	bool
	help
	  Enable this for PMC devices where the reset configuration
	  and lock register is located under PMC BASE at offset ETR.
	  Note that the reset register is still at 0xCF9 this only
	  controls the enable and lock feature.