config SOC_INTEL_SKYLAKE bool help Intel Skylake support config SOC_INTEL_KABYLAKE bool default n select SOC_INTEL_SKYLAKE help Intel Kabylake support if SOC_INTEL_SKYLAKE config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_NHLT select ARCH_BOOTBLOCK_X86_32 select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 select BOOTBLOCK_CONSOLE select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COLLECT_TIMESTAMPS select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select C_ENVIRONMENT_BOOTBLOCK select GENERIC_GPIO_LIB select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select INTEL_GMA_ACPI select IOAPIC select MRC_SETTINGS_PROTECT select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PARALLEL_MP_AP_WORK select PCIEXP_ASPM select PCIEXP_CLK_PM select PCIEXP_COMMON_CLOCK select PCIEXP_L1_SUB_STATE select PCIEX_LENGTH_64MB select REG_SCRIPT select RTC select SA_ENABLE_DPR select SMM_TSEG select SMP select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_GSPI select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SGX select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_VMX select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC select FSP_T_XIP if FSP_CAR config CPU_INTEL_NUM_FIT_ENTRIES int default 10 config MAINBOARD_USES_FSP2_0 bool default n config USE_FSP2_0_DRIVER def_bool y depends on MAINBOARD_USES_FSP2_0 select PLATFORM_USES_FSP2_0 select UDK_2015_BINDING select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select POSTCAR_CONSOLE select POSTCAR_STAGE config USE_FSP1_1_DRIVER def_bool y depends on !MAINBOARD_USES_FSP2_0 select PLATFORM_USES_FSP1_1 select DISPLAY_FSP_ENTRY_POINTS config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC config VBOOT select VBOOT_EC_SLOW_UPDATE if VBOOT_EC_SOFTWARE_SYNC select VBOOT_SEPARATE_VERSTAGE select VBOOT_OPROM_MATTERS select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH config BOOTBLOCK_RESETS string default "soc/intel/common/reset.c" config CBFS_SIZE hex default 0x200000 config CPU_ADDR_BITS int default 36 config DCACHE_RAM_BASE hex default 0xfef00000 config DCACHE_RAM_SIZE hex default 0x40000 help The size of the cache-as-ram region required during bootblock and/or romstage. config DCACHE_BSP_STACK_SIZE hex default 0x4000 help The amount of anticipated stack usage in CAR by bootblock and other stages. config C_ENV_BOOTBLOCK_SIZE hex default 0xC000 config EXCLUDE_NATIVE_SD_INTERFACE bool default n help If you set this option to n, will not use native SD controller. config HEAP_SIZE hex default 0x80000 config IED_REGION_SIZE hex default 0x400000 config PCR_BASE_ADDRESS hex default 0xfd000000 help This option allows you to select MMIO Base Address of sideband bus. config SERIRQ_CONTINUOUS_MODE bool default n help If you set this option to y, the serial IRQ machine will be operated in continuous mode. config SMM_RESERVED_SIZE hex default 0x200000 config SMM_TSEG_SIZE hex default 0x800000 config VGA_BIOS_ID string default "8086,0406" config UART_DEBUG bool "Enable UART debug port." default n select CONSOLE_SERIAL select DRIVERS_UART select DRIVERS_UART_8250MEM_32 select NO_UART_ON_SUPERIO config UART_FOR_CONSOLE int "Index for LPSS UART port to use for console" default 2 if DRIVERS_UART_8250MEM default 0 help Index for LPSS UART port to use for console: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 config SKYLAKE_SOC_PCH_H bool default n help Choose this option if you have a PCH-H chipset. config CHIPSET_BOOTBLOCK_INCLUDE string default "soc/intel/skylake/bootblock/timestamp.inc" config NHLT_DMIC_2CH bool default n help Include DSP firmware settings for 2 channel DMIC array. config NHLT_DMIC_4CH bool default n help Include DSP firmware settings for 4 channel DMIC array. config NHLT_NAU88L25 bool default n help Include DSP firmware settings for nau88l25 headset codec. config NHLT_MAX98357 bool default n help Include DSP firmware settings for max98357 amplifier. config NHLT_MAX98373 bool default n help Include DSP firmware settings for max98373 amplifier. config NHLT_SSM4567 bool default n help Include DSP firmware settings for ssm4567 smart amplifier. config NHLT_RT5514 bool default n help Include DSP firmware settings for rt5514 DSP. config NHLT_RT5663 bool default n help Include DSP firmware settings for rt5663 headset codec. config NHLT_MAX98927 bool default n help Include DSP firmware settings for max98927 amplifier. config NHLT_DA7219 bool default n help Include DSP firmware settings for DA7219 headset codec. choice prompt "Cache-as-ram implementation" default USE_SKYLAKE_CAR_NEM_ENHANCED help This option allows you to select how cache-as-ram (CAR) is set up. config USE_SKYLAKE_CAR_NEM_ENHANCED bool "Enhanced Non-evict mode" select SOC_INTEL_COMMON_BLOCK_CAR select INTEL_CAR_NEM_ENHANCED help A current limitation of NEM (Non-Evict mode) is that code and data sizes are derived from the requirement to not write out any modified cache line. With NEM, if there is no physical memory behind the cached area, the modified data will be lost and NEM results will be inconsistent. ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. config USE_SKYLAKE_FSP_CAR bool "Use FSP CAR" select FSP_CAR help Use FSP APIs to initialize and tear down the Cache-As-Ram. endchoice config FSP_HEADER_PATH string "Location of FSP headers" depends on MAINBOARD_USES_FSP2_0 # Use KabylakeFsp for both Skylake and Kabylake as it supports both. # SkylakeFsp is FSP 1.1 and therefore incompatible. default "3rdparty/fsp/KabylakeFspBinPkg/Include/" if SOC_INTEL_SKYLAKE default "3rdparty/fsp/KabylakeFspBinPkg/Include/" if SOC_INTEL_KABYLAKE config FSP_FD_PATH string depends on FSP_USE_REPO default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_SKYLAKE default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_KABYLAKE config SKIP_FSP_CAR bool "Skip cache as RAM setup in FSP" default y help Skip Cache as RAM setup in FSP. config SPI_FLASH_INCLUDE_ALL_DRIVERS bool default n config MAX_ROOT_PORTS int default 24 if PLATFORM_USES_FSP2_0 default 20 if PLATFORM_USES_FSP1_1 config NO_FADT_8042 bool default n help Choose this option if you want to disable 8042 Keyboard config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 120 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int default 2 config SOC_INTEL_I2C_DEV_MAX int default 6 config CPU_BCLK_MHZ int default 100 # Clock divider parameters for 115200 baud rate config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex default 0x30 config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL hex default 0xc35 config IFD_CHIPSET string default "sklkbl" endif