# This file is part of the coreboot project.
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.

config SOC_SIFIVE_FU540
	bool
	select ARCH_RISCV_RV64
	select ARCH_RISCV_S
	select ARCH_RISCV_U
	select ARCH_RISCV_PMP
	select ARCH_BOOTBLOCK_RISCV
	select ARCH_VERSTAGE_RISCV
	select ARCH_ROMSTAGE_RISCV
	select ARCH_RAMSTAGE_RISCV
	select DRIVERS_UART_SIFIVE
	select RISCV_USE_ARCH_TIMER
	select UART_OVERRIDE_REFCLK
	select RISCV_HAS_OPENSBI

if SOC_SIFIVE_FU540

config RISCV_ARCH
	string
	default "rv64imac"

config RISCV_ABI
	string
	default "lp64"

config RISCV_CODEMODEL
	string
	default "medany"

config MAX_CPUS
	int
	default 5

config RISCV_WORKING_HARTID
	int
	default 0

config OPENSBI_PLATFORM
	string
	default "sifive/fu540"

config OPENSBI_TEXT_START
	hex
	default 0x80000000
endif