# This file is part of the coreboot project.
# SPDX-License-Identifier: GPL-2.0-only

config SOUTHBRIDGE_AMD_CIMX_SB800
	bool
	default n
	select IOAPIC
	select HAVE_USBDEBUG_OPTIONS
	select AMD_SB_CIMX
	select HAVE_CF9_RESET
	select HAVE_CF9_RESET_PREPARE
	select SOC_AMD_COMMON
	select SOC_AMD_COMMON_BLOCK
	select SOC_AMD_COMMON_BLOCK_ACPIMMIO

if SOUTHBRIDGE_AMD_CIMX_SB800
config ENABLE_IDE_COMBINED_MODE
	bool "Enable SATA IDE combined mode"
	default n
	help
	  If Combined Mode is enabled. IDE controller is exposed and
	  SATA controller has control over Port0 through Port3,
	  IDE controller has control over Port4 and Port5.

	  If Combined Mode is disabled, IDE controller is hidden and
	  SATA controller has full control of all 6 Ports when operating in non-IDE mode.

config IDE_COMBINED_MODE
	hex
	default 0x0 if ENABLE_IDE_COMBINED_MODE
	default 0x1 if !ENABLE_IDE_COMBINED_MODE

choice
	prompt "SATA Mode"
	default SB800_SATA_AHCI
	help
	  Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
	  The default is AHCI.

config SB800_SATA_IDE
	bool "NATIVE"
	help
	  NATIVE does not require a ROM.

config SB800_SATA_AHCI
	bool "AHCI"
	help
	  AHCI is the default and may work with or without AHCI ROM. It depends on the payload support.
	  For example, seabios does not require the AHCI ROM.

config SB800_SATA_RAID
	bool "RAID"
	help
	  sb800 RAID mode must have the two required ROM files.

endchoice

config SB800_SATA_MODE
	hex
	depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI)
	default 0x0 if SB800_SATA_IDE
	default 0x1 if SB800_SATA_RAID
	default 0x2 if SB800_SATA_AHCI

config SB_SUPERIO_HWM
	bool
	default n

if SB800_SATA_AHCI
config AHCI_ROM_ID
	string "AHCI device PCI IDs"
	default "1002,4391"

config SB800_AHCI_ROM
	bool "Add a AHCI ROM"

config AHCI_ROM_FILE
	string "AHCI ROM path and filename"
	depends on SB800_AHCI_ROM
	default "site-local/sb800/ahci.bin"
endif

if SB800_SATA_RAID
config RAID_ROM_ID
	string "RAID device PCI IDs"
	default "1002,4393"
	help
	  1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode

config RAID_ROM_FILE
	string "RAID ROM path and filename"
	depends on SB800_SATA_RAID
	default "site-local/sb800/raid.bin"

config RAID_MISC_ROM_FILE
	string "RAID Misc ROM path and filename"
	default "site-local/sb800/misc.bin"
	depends on SB800_SATA_RAID

config RAID_MISC_ROM_POSITION
	hex "RAID Misc ROM Position"
	default 0xFFF00000
	depends on SB800_SATA_RAID
	help
	  The RAID ROM requires that the MISC ROM is located between the range
	  0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
	  The CONFIG_ROM_SIZE must larger than 0x100000.

endif

config SB800_IMC_FWM
	bool "Add IMC firmware"
	default n
	select SPI_FLASH_HAS_VOLATILE_GROUP if SPI_FLASH
	help
	  Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control.

if SB800_IMC_FWM

config SB800_IMC_FWM_FILE
	string "IMC firmware path and filename"
	default "3rdparty/blobs/southbridge/amd/sb800/imc.bin"

choice
	prompt "SB800 Firmware ROM Position"

config SB800_FWM_AT_FFFA0000
	bool "0xFFFA0000"
	help
	  The IMC and GEC ROMs requires a 'signature' located at one of several
	  fixed locations in memory.  The location used shouldn't matter, just
	  select an area that doesn't conflict with anything else.

config SB800_FWM_AT_FFF20000
	bool "0xFFF20000"
	help
	  The IMC and GEC ROMs requires a 'signature' located at one of several
	  fixed locations in memory.  The location used shouldn't matter, just
	  select an area that doesn't conflict with anything else.

config SB800_FWM_AT_FFE20000
	depends on BOARD_ROMSIZE_KB_8192 || BOARD_ROMSIZE_KB_4096 || BOARD_ROMSIZE_KB_2048
	bool "0xFFE20000"
	help
	  The IMC and GEC ROMs requires a 'signature' located at one of several
	  fixed locations in memory.  The location used shouldn't matter, just
	  select an area that doesn't conflict with anything else.

config SB800_FWM_AT_FFC20000
	depends on BOARD_ROMSIZE_KB_8192 || BOARD_ROMSIZE_KB_4096
	bool "0xFFC20000"
	help
	  The IMC and GEC ROMs requires a 'signature' located at one of several
	  fixed locations in memory.  The location used shouldn't matter, just
	  select an area that doesn't conflict with anything else.

config SB800_FWM_AT_FF820000
	depends on BOARD_ROMSIZE_KB_8192
	bool "0xFF820000"
	help
	  The IMC and GEC ROMs requires a 'signature' located at one of several
	  fixed locations in memory.  The location used shouldn't matter, just
	  select an area that doesn't conflict with anything else.

endchoice

config SB800_FWM_POSITION
	hex
	default 0xFFFA0000 if SB800_FWM_AT_FFFA0000
	default 0xFFF20000 if SB800_FWM_AT_FFF20000
	default 0xFFE20000 if SB800_FWM_AT_FFE20000
	default 0xFFC20000 if SB800_FWM_AT_FFC20000
	default 0xFF820000 if SB800_FWM_AT_FF820000

endif  #SB800_IMC_FWM

config EHCI_BAR
	hex
	default 0xfef00000

choice
	prompt "Fan Control"
	default SB800_NO_FAN_CONTROL
	help
	  Select the method of SB800 fan control to be used.  None would be
	  for either fixed maximum speed fans connected to the SB800 or for
	  an external chip controlling the fan speeds.  Manual control sets
	  up the SB800 fan control registers.  IMC fan control uses the SB800
	  IMC to actively control the fan speeds.

config SB800_NO_FAN_CONTROL
	bool "None"
	help
	  No SB800 Fan control - Do not set up the SB800 fan control registers.

config SB800_MANUAL_FAN_CONTROL
	bool "Manual"
	help
	  Configure the SB800 fan control registers in devicetree.cb.

config SB800_IMC_FAN_CONTROL
	bool "IMC Based"
	depends on SB800_IMC_FWM
	help
	  Set up the SB800 to use the IMC based Fan controller.  This requires
	  the IMC ROM from AMD.  Configure the registers in devicetree.cb.

endchoice

endif #SOUTHBRIDGE_AMD_CIMX_SB800