/* SPDX-License-Identifier: GPL-2.0-or-later */
/* This file is part of the coreboot project. */

#ifndef SUPERIO_WINBOND_W83627UHG_W83627UHG_H
#define SUPERIO_WINBOND_W83627UHG_W83627UHG_H

#define W83627UHG_FDC			0   /* Floppy */
#define W83627UHG_PP			1   /* Parallel port */
#define W83627UHG_SP1			2   /* Com1 */
#define W83627UHG_SP2			3   /* Com2 */
#define W83627UHG_KBC			5   /* PS/2 keyboard & mouse */
#define W83627UHG_SP3			6   /* Com3 */
#define W83627UHG_GPIO3_4		7   /* GPIO 3/4 */
#define W83627UHG_WDTO_PLED_GPIO5_6	8   /* WDTO#, PLED, GPIO5/6 */
#define W83627UHG_GPIO1_2		9   /* GPIO 1/2, SUSLED */
#define W83627UHG_ACPI			10  /* ACPI */
#define W83627UHG_HWM			11  /* Hardware monitor */
#define W83627UHG_PECI_SST		12  /* PECI, SST */
#define W83627UHG_SP4			13  /* Com4 */
#define W83627UHG_SP5			14  /* Com5 */
#define W83627UHG_SP6			15  /* Com6 */

#endif /* SUPERIO_WINBOND_W83627UHG_W83627UHG_H */