/* $NoKeywords:$ */ /** * @file * * Create outline and references for GNB Component mainpage documentation. * * Design guides, maintenance guides, and general documentation, are * collected using this file onto the documentation mainpage. * This file contains doxygen comment blocks, only. * * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: Documentation * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ * */ /* ****************************************************************************** * * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. * * AMD is granting you permission to use this software (the Materials) * pursuant to the terms and conditions of your Software License Agreement * with AMD. This header does *NOT* give you permission to use the Materials * or any rights under AMD's intellectual property. Your use of any portion * of these Materials shall constitute your acceptance of those terms and * conditions. If you do not agree to the terms and conditions of the Software * License Agreement, please do not use any portion of these Materials. * * CONFIDENTIALITY: The Materials and all other information, identified as * confidential and provided to you by AMD shall be kept confidential in * accordance with the terms and conditions of the Software License Agreement. * * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. * * AMD does not assume any responsibility for any errors which may appear in * the Materials or any other related information provided to you by AMD, or * result from use of the Materials or any related information. * * You agree that you will not reverse engineer or decompile the Materials. * * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any * further information, software, technical information, know-how, or show-how * available to you. Additionally, AMD retains the right to modify the * Materials at any time, without notice, and is not obligated to provide such * modified Materials to you. * * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is * subject to the restrictions as set forth in FAR 52.227-14 and * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the * Government constitutes acknowledgement of AMD's proprietary rights in them. * * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any * direct product thereof will be exported directly or indirectly, into any * country prohibited by the United States Export Administration Act and the * regulations thereunder, without the required authorization from the U.S. * government nor will be used for any purpose prohibited by the same. ****************************************************************************** */ /** * @page gnbmain GNB Component Documentation * * Additional documentation for the GNB component consists of * * - Maintenance Guides: * - @subpage F12PcieLaneDescription "Family 0x12 PCIe/DDI Lane description table" * - @subpage F14ONPcieLaneDescription "Family 0x14(ON) PCIe/DDI Lane description table" * - @subpage F12LaneConfigurations "Family 0x12 PCIe port/DDI link configurations" * - @subpage F14ONLaneConfigurations "Family 0x14(ON) PCIe port/DDI link configurations" * - @subpage F12DualLinkDviDescription "Family 0x12 Dual Link DVI connector description" * - add here >>> * - Design Guides: * - @subpage BuildConfigDescription "Build Configurations" * - add here >>> * */ /** * @page F12PcieLaneDescription Family 0x12 PCIe/DDI Lanes * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Lane IDLane groupPin
0 SB P_SB_RX[P/N]/TX[P/N][0]
1 SB P_SB_RX[P/N]/TX[P/N][1]
2 SB P_SB_RX[P/N]/TX[P/N][2]
3 SB P_SB_RX[P/N]/TX[P/N][3]
4 GPPP_GPP_RX[P/N]/TX[P/N][0]
5 GPPP_GPP_RX[P/N]/TX[P/N][1]
6 GPPP_GPP_RX[P/N]/TX[P/N][2]
7 GPPP_GPP_RX[P/N]/TX[P/N][3]
8 GFXP_GFX_RX[P/N]/TX[P/N][0]
9 GFXP_GFX_RX[P/N]/TX[P/N][1]
10GFXP_GFX_RX[P/N]/TX[P/N][2]
11GFXP_GFX_RX[P/N]/TX[P/N][3]
12GFXP_GFX_RX[P/N]/TX[P/N][4]
13GFXP_GFX_RX[P/N]/TX[P/N][5]
14GFXP_GFX_RX[P/N]/TX[P/N][6]
15GFXP_GFX_RX[P/N]/TX[P/N][7]
16GFXP_GFX_RX[P/N]/TX[P/N][8]
17GFXP_GFX_RX[P/N]/TX[P/N][9]
18GFXP_GFX_RX[P/N]/TX[P/N][10]
19GFXP_GFX_RX[P/N]/TX[P/N][11]
20GFXP_GFX_RX[P/N]/TX[P/N][12]
21GFXP_GFX_RX[P/N]/TX[P/N][13]
22GFXP_GFX_RX[P/N]/TX[P/N][14]
23GFXP_GFX_RX[P/N]/TX[P/N][15]
24DDIDP1_TXP/N[0]
25DDIDP1_TXP/N[1]
26DDIDP1_TXP/N[2]
27DDIDP1_TXP/N[3]
28DDIDP0_TXP/N[0]
29DDIDP0_TXP/N[1]
30DDIDP0_TXP/N[2]
31DDIDP0_TXP/N[3]
* */ /** * @page F14ONPcieLaneDescription Family 0x14(ON) PCIe/DDI Lanes * * * * * * * * * * * * * * * * * * *
Lane IDLane groupPin
0 SB P_SB_RX[P/N]/TX[P/N][0]
1 SB P_SB_RX[P/N]/TX[P/N][1]
2 SB P_SB_RX[P/N]/TX[P/N][2]
3 SB P_SB_RX[P/N]/TX[P/N][3]
4 GPPP_GPP_RX[P/N]/TX[P/N][0]
5 GPPP_GPP_RX[P/N]/TX[P/N][1]
6 GPPP_GPP_RX[P/N]/TX[P/N][2]
7 GPPP_GPP_RX[P/N]/TX[P/N][3]
8DDIDP0_TXP/N[0]
9DDIDP0_TXP/N[1]
10DDIDP0_TXP/N[2]
11DDIDP0_TXP/N[3]
12DDIDP1_TXP/N[0]
13DDIDP1_TXP/N[1]
14DDIDP1_TXP/N[2]
15DDIDP1_TXP/N[3]
* */ /** * @page F12DualLinkDviDescription Family 0x12 Dual Link DVI connector description * Examples of various Dual Link DVI descriptors. * @code * // Dual Link DVI on dedicated display lanes. DP1_TXP/N[0]..DP1_TXP/N[3] - master, DP0_TXP/N[0]..DP0_TXP/N[3] - slave. * PCIe_PORT_DESCRIPTOR DdiList [] = { * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 32), * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * } * } * // Dual Link DVI on dedicated display lanes. DP0_TXP/N[0]..DP0_TXP/N[3] - master, DP1_TXP/N[0]..DP1_TXP/N[3] - slave. * PCIe_PORT_DESCRIPTOR DdiList [] = { * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 24), * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * } * } * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - master, P_GFX_TXP/N[4]..P_GFX_TXP/N[7] - slave. * PCIe_PORT_DESCRIPTOR DdiList [] = { * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 15), * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * } * } * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[7]..P_GFX_TXP/N[4] - master, P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - slave. * PCIe_PORT_DESCRIPTOR DdiList [] = { * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 15, 8), * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * } * } * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - master, P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - slave. * PCIe_PORT_DESCRIPTOR DdiList [] = { * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 23), * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * } * } * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - master, P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - slave. * PCIe_PORT_DESCRIPTOR DdiList [] = { * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 23, 16), * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) * } * } * @endcode */ /** * @page F12LaneConfigurations Family 0x12 PCIe port/DDI link configurations *
* *

PCIe port * configurations for lane 8 through 23.

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
*

Configuration

* 		*

PCIe Port Device Number

* 		*

Start Lane (Start Lane in reverse * configuration)

* 		*

End Line (End lane in reverse * configuration)

*
*

Config A*

* 		*

2

*

 

* 		*

8(23)

* 		*

23(8)

*
*

8(15)

* 		*

15(8)

*
*

8(11)

* 		*

11(8)

*
*

8(9)

* 		*

9(8)

*
*

10(11)

* 		*

11(10)

*
*

12(15)

* 		*

15(12)

*
*

12(13)

* 		*

13(12)

*
*

14(15)

* 		*

15(14)

*
*

16(23)

* 		*

23(16)

*
*

16(19)

* 		*

19(16)

*
*

16(17)

* 		*

17(16)

*
*

18(19)

* 		*

19(18)

*
*

20(23)

* 		*

23(20)

*
*

20(21)

* 		*

21(20)

*
*

22(23)

* 		*

23(22)

*
*

3

*

 

* 		*

8(15)

* 		*

15(8)

*
*

8(11)

* 		*

11(8)

*
*

8(9)

* 		*

9(8)

*
*

10(11)

* 		*

11(10)

*
*

12(15)

* 		*

15(12)

*
*

12(13)

* 		*

13(12)

*
*

14(15)

* 		*

15(14)

*
*

16(23)

* 		*

23(16)

*
*

16(19)

* 		*

19(16)

*
*

16(17)

* 		*

17(16)

*
*

18(19)

* 		*

19(18)

*
*

20(23)

* 		*

23(20)

*
*

20(21)

* 		*

21(20)

*
*

22(23)

* 		*

23(22)

*
*

* Lanes selection for port 2/3 should not overlap in port configuration

*
* *

 

* *

PCIe port * configurations for lane 4 through 7.

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
*

Configuration

* 		*

PCIe Port Device Number

* 		*

Start Lane (Start Lane in reverse * configuration)

* 		*

End Line (End lane in reverse * configuration)

*
*

Config A

* 		*

4

* 		*

4(7)

* 		*

7(4)

*
*

4(5)

* 		*

5(4)

*
*

4

* 		*

4

*
*

Config B

* 		*

4

* 		*

4(5)

* 		*

5(4)

*
*

4

* 		*

4

*
*

5 or 6

* 		*

6(7)

* 		*

7(6)

*
*

6

* 		*

6

*
*

Config C

* 		*

4

* 		*

4(5)

* 		*

5(4)

*
*

4

* 		*

4

*
*

5 or 6

* 		*

6

* 		*

6

*
*

6 or 7

* 		*

7

* 		*

7

*
*

Config D

* 		*

4

* 		*

4

* 		*

4

*
*

5

* 		*

5

* 		*

5

*
*

6

* 		*

6

* 		*

6

*
*

7

* 		*

7

* 		*

7

*
* *

 

* *

DDI link * configurations for lanes 24 through 31.

* * * * * * * * * * * * * * * * * * * * * * * * * *
*

Configuration

* 		*

Connector type

* 		*

Start Lane (Start Lane in reverse * configuration)

* 		*

End Line (End lane in reverse * configuration)

*
*

Config A

* 		*

Dual Link DVI-D

* 		*

24(31)

* 		*

31(24)

*
*

Config B

* 		*

HDMI

*

Single Link DVI-D

*

DP

*

eDP

*

Travis DP-to-CRT

*

Travis DP-to-LVDS

*

Hudson2 DP-to-CRT

* 		*

24

* 		*

27

*
*

HDMI

*

Single Link DVI-D

*

DP

*

eDP

*

Travis DP-to-CRT

*

Travis DP-to-LVDS

*

Hudson2 DP-to-CRT

* 		*

28

* 		*

31

*
* *

 

* *

DDI link * configurations for lanes 8 through 23.

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
*

Configuration

* 		*

Connector type

* 		*

Start Lane (Start Lane in reverse * configuration)

* 		*

End Line (End lane in reverse * configuration)

*
*

Config A

* 		*

Dual Link DVI-D

* 		*

8(15)

* 		*

15(8)

*
*

Dual Link DVI-D

* 		*

16(23)

* 		*

23(16)

*
*

Config B

* 		*

Dual Link DVI-D

* 		*

8(15)

* 		*

15(8)

*
*

HDMI

*

Single Link DVI-D

*

DP

*

eDP

*

Travis DP-to-CRT

*

Travis DP-to-LVDS

*

Hudson2 DP-to-CRT

* 		*

16

* 		*

19

*
*

HDMI

*

Single Link DVI-D

*

DP

*

eDP

*

Travis DP-to-CRT

*

Travis DP-to-LVDS

*

Hudson2 DP-to-CRT

* 		*

20

* 		*

23

*
*

Config C

* 		*

HDMI

*

Single Link DVI-D

*

DP

*

eDP

*

Travis DP-to-CRT

*

Travis DP-to-LVDS

*

Hudson2 DP-to-CRT

* 		*

8

* 		*

11

*
*

HDMI

*

Single Link DVI-D

*

DP

*

eDP

*

Travis DP-to-CRT

*

Travis DP-to-LVDS

*

Hudson2 DP-to-CRT

* 		*

12

* 		*

15

*
*

Dual Link DVI-D

* 		*

16(23)

* 		*

23(16)

*
*

Config D

* 		*

HDMI

*

Single Link DVI-D

*

DP

*

eDP

*

Travis DP-to-CRT

*

Travis DP-to-LVDS

*

Hudson2 DP-to-CRT

* 		*

8

* 		*

11

*
*

HDMI

*

Single Link DVI-D

*

DP

*

eDP

*

Travis DP-to-CRT

*

Travis DP-to-LVDS

*

Hudson2 DP-to-CRT

* 		*

12

* 		*

15

*
*

HDMI

*

Single Link DVI-D

*

DP

*

eDP

*

Travis DP-to-CRT

*

Travis DP-to-LVDS

*

Hudson2 DP-to-CRT

* 		*

16

* 		*

19

*
*

HDMI

*

Single Link DVI-D

*

DP

*

eDP

*

Travis DP-to-CRT

*

Travis DP-to-LVDS

*

Hudson2 DP-to-CRT

* 		*

20

* 		*

23

*
* *

 

*
*/ /** * @page F14ONLaneConfigurations Family 0x14(ON) PCIe port/DDI link configurations *
*

PCIe port * configurations for lane 4 through 7.

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
*

Configuration

* 		*

PCIe Port Device Number

* 		*

Start Lane (Start Lane in reverse * configuration)

* 		*

End Line (End lane in reverse * configuration)

*
*

Config A

* 		*

4

* 		*

4(7)

* 		*

7(4)

*
*

4(5)

* 		*

5(4)

*
*

4

* 		*

4

*
*

Config B

* 		*

4

* 		*

4(5)

* 		*

5(4)

*
*

4

* 		*

4

*
*

5 or 6

* 		*

6(7)

* 		*

7(6)

*
*

6

* 		*

6

*
*

Config C

* 		*

4

* 		*

4(5)

* 		*

5(4)

*
*

4

* 		*

4

*
*

5 or 6

* 		*

6

* 		*

6

*
*

6 or 7

* 		*

7

* 		*

7

*
*

Config D

* 		*

4

* 		*

4

* 		*

4

*
*

5

* 		*

5

* 		*

5

*
*

6

* 		*

6

* 		*

6

*
*

7

* 		*

7

* 		*

7

*
* *

 

* *

CRT/DDI link * configurations for lanes 8 through 19.

* * * * * * * * * * * * * * * * * * * * * * * * * * * *
*

Configuration

* 		*

Connector type

* 		*

Start Lane (Start Lane in reverse * configuration)

* 		*

End Line (End lane in reverse * configuration)

*
*

Config A

* 		*

HDMI

*

Single Link DVI-D

*

Single Link DVI-I*

*

DP

*

eDP

*

Travis DP-to-CRT

*

Travis DP-to-LVDS

*

Hudson2 DP-to-CRT

* 		*

8

* 		*

11

*
*

HDMI

*

Single Link DVI-D

*

Single Link DVI-I*

*

DP

*

eDP

*

Travis DP-to-CRT

*

Travis DP-to-LVDS

*

Hudson2 DP-to-CRT

* 		*

12

* 		*

15

*
*

CRT*

* 		*

16

* 		*

19

*
*

* - Only one connector of this time can exist in configuration

*
* *

 

* *

 

* *
*/ /** * @page BuildConfigDescription GNB Build Configurations. * * Build configurations are configuration constants. The purpose * of build configurations is to specify configuration info * regarding the GNB component. * * The documented build configurations are imported from a user * controlled file for processing. The build configurations for * all platform solutions are listed below: * * @anchor BLDCFG_USE_SYNCFLOOD_AS_NMI * @li @e BLDCFG_USE_SYNCFLOOD_AS_NMI @n * This build configuration defines the function of the * SYNCFLOOD/NMI# pin. If TRUE, then the pin is defined * as NMI#. If FALSE or undefined, the pin is defined as * SYNCFLOOD_L. * */